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rev. 2.7 june 2003 1/158 st72589bw, st72389bw 8-bit mcu with nested interrupts, dot matrix lcd, adc, timers, pwm-brm, spi, sci, i2c, can interfaces datasheet n 16k rom or 24 kbytes eprom/otp/ fastrom n master reset and power-on reset n low consumption resonator main oscillator n 4 power saving modes n nested interrupt controller n nmi dedicated non maskable interrupt pin n 31 multifunctional bidirectional i/o lines with: C external interrupt capability (5 vectors) C 21 alternate function lines n lcd driver with 60 segment outputs and 8 backplane outputs able to drive up to 60x8 (480) or 60x4 (240) lcd displays n real time base, beep and clock-out capabilities n software watchdog reset n two 16-bit timers with: C 2 input captures C 2 output compares C external clock input on one timer C pwm and pulse generator modes n 10-bit pwm (dac) with 4 dedicated output pins n spi synchronous serial interface n sci asynchronous serial interface n i2c multi master / slave interface n can interface n 8-bit adc with 5 dedicated input pins n 8-bit data manipulation n 63 basic instructions n 17 main addressing modes n 8 x 8 unsigned multiply instruction n true bit manipulation n full hardware/software development package device summary pqfp128 14 x 20 features st72589bw5 st72389bw4 program memory - bytes 24k otp/fastrom 16k rom ram (stack) - bytes 1024 (256) 512 (256) std. peripherals lcd 60x8, watchdog, 16-bit timers, pwm-brm, spi, sci, i2c, can, adc lcd 60x8, watchdog, 16-bit timers, spi, sci, adc operating supply 4.5v to 5.5v cpu frequency 4 to 8 mhz (with 8 to 16 mhz oscillator) temperature range -40c to +85c packages pqfp128 development device st72e589bw5 1
table of contents 158 2/158 2 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 memories and programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 reset manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 3.2 low consumption oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 main clock controller (mcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 interrupts & power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1 i/o port interrupt sensitivity description . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 i/o port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 miscellaneous registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.4 pwm/brm generator (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.6 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.7 i2c bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.9 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.3 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
table of contents 3/158 3 9.5 i/o ports characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6 supply, reset and clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.7 memory and peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 154 11.1 ordering information and transfer of customer code . . . . . . . . . . . . 154 11.2 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
st72589bw, st72389bw 4/158 1 general description 1.1 introduction the st72589w and st72389w microcontroller units are members of the st7 family of microcon- trollers dedicated to high-end applications with lcd driver capability. these devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. under software control, these microcontrollers may be placed in either wait, slow, active- halt or halt modes, thus reducing power con- sumption. the enhanced instruction set and addressing modes afford real programming potential. in addi- tion to standard 8-bit data management, these mi- crocontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. figure 1. device block diagram 8-bit core alu address and data bus osc2 osc1 reset main osc control eprom 24k v dd nmi port c pc0 -> pc7 (8-bit) sci beep timer a ram 512 or 1k power supply v ss watchdog pwm-brm* 8-bit adc pwm0 -> pwm3 (4-bit) ain0 -> ain4 (5-channel) v dda v ssa port b pb0 -> pb6 (7-bit) timer b can* port d pd0 -> pd7 (8-bit) spi i2c* lcd driver + lcd ram (60x8) s1 -> s60 (60-segment) com1 -> com8 (60-common) glcd vlcd, vlcd3/4, vlcd1/2, vlcd1/4 port a pa0 -> pa7 (8-bit) *available on st72589 version only 4
st72589bw, st72389bw 5/158 1.2 pin description figure 2. 128-pin pqfp package pinout 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s49 s50 s51 s52 s53 s54 s55 s56 s57 s58 s59 s60 s45 s46 s47 s48 s40 s39 s38 s37 s36 s35 s34 s33 s32 s31 s30 s29 s44 s43 s42 s41 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v lcd v dd_a ain0 ain1 ain2 ain3 ain4 v ss_a pwm0* pwm1* pwm2* pwm3* g lcd v lcd1/4 v lcd1/2 v lcd3/4 33 34 35 36 37 38 reset vpp v dd_1 osc1 osc2 v ss_1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 ei5 ei5 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s18 s17 s16 s15 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 com6 com5 com4 com3 com2 com1 v dd_3 v ss v ss v ss_3 pd7 pd6 s2 s1 com8 com7 70 69 68 67 66 65 pd5 / sdai* pd4 / scli* pd3 / ss pd2 / sck pd1 / mosi pd0 / miso 112 111 110 109 108 107 106 105 104 103 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 icap2_a / pc3 icap1_a / pc2 rdi / pc1 tdo / pc0 v ss_2 v dd_2 can_rx */ pb6 can_rx* / pb5 pb4 icap2_b / pb3 icap1_b / pb2 ocmp2_b / pb1 mco / beep / pc7 clk_a / pc6 ocmp2_a / pc5 ocmp1_a / pc4 48 47 46 45 44 43 42 41 40 39 ocmp1_b / pb0 nmi pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ei4 ei3 ei2 ei1 5
st72589bw, st72389bw 6/158 pin description (contd) legend / abbreviations: type: i = input, o = output, s = supply, ck = clock output level: lcd = v lcd , v lcd3/4 , v lcd1/2 , v lcd1/4 , or g lcd level. input level: c = cmos 0.3v dd /0.7v dd port configuration capabilities: C input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog C output: od = open drain, t = true open drain, pp = push-pull note: reset configuration of each pin is bold. table 1. device pin description pin n pin name type level port main func tion (after reset) alternate function pqfp128 input output input output float wpu int ana od pp 1 ... 16 s45 ... s60 o lcd lcd segment analog outputs 17 g lcd s lcd ground reference voltage 18 v lcd1/4 s lcd supply reference voltage 19 v lcd1/2 s 20 v lcd3/4 s 21 v lcd s 22 v dda s analog power supply voltage 23 ain0 i x adc analog input 0 24 ain1 i x adc analog input 1 25 ain2 i x adc analog input 2 26 ain3 i x adc analog input 3 27 ain4 i x adc analog input 4 28 v ssa s analog ground voltage 29 pwm0* or nc o pulse width modulator output 0* 30 pwm1*or nc o pulse width modulator output 1* 31 pwm2* or nc o pulse width modulator output 2* 32 pwm3* or nc o pulse width modulator output 3* 33 reset i/o top priority non maskable interrupt. 34 v pp i must be tied low in user mode. in the pro- gramming mode when available, this pin acts as the programming voltage input v pp . 35 v dd_1 s digital main supply voltage 36 osc1 ck these pins connect a parallel-resonant crystal or an external source to the on-chip main oscillator. 37 osc2 ck 38 v ss_1 s digital ground voltage 39 pa0 i/o c x ei1 x x port a0 40 pa1 i/o c x x x port a1 41 pa2 i/o c x x x port a2 42 pa3 i/o c x x x port a3 6
st72589bw, st72389bw 7/158 * available on st72589 version only. ** available on st72589 version only. port d4 and d5 in open-drain output only for st72589. 43 pa4 i/o c x ei2 x x port a4 44 pa5 i/o c x x x port a5 45 pa6 i/o c x x x port a6 46 pa7 i/o c x x x port a7 47 nmi i no maskable interrupt input pin (floating) 48 pb0/ocmp1_b i/o c x ei3 x x port b0 timer b output compare 1 49 pb1/ocmp2_b i/o c x x x port b1 timer b output compare 2 50 pb2/icap1_b i/o c x x x port b2 timer b input capture 1 51 pb3/icap2_b i/o c x x x port b3 timer b input capture 2 52 pb4 i/o c x x x port b4 53 pb5/cantx* i/o c x x x port b5 can transmit data output* 54 pb6/canrx* i/o c x x x port b6 can receive data input* 55 v dd_2 s digital main supply voltage 56 v ss_2 s digital ground voltage 57 pc0/tdo i/o c x ei4 x x port c0 sci transmit data out 58 pc1/rdi i/o c x x x port c1 sci receive data in 59 pc2/icap1_a i/o c x x x port b2 timer a input capture 1 60 pc3/icap2_a i/o c x x x port b3 timer a input capture 2 61 pc4/ocmp1_a i/o c x x x port b0 timer a output compare 1 62 pc5/ocmp2_a i/o c x x x port b1 timer a output compare 2 63 pc6/extclk_a i/o c x x x port c6 timer a external clock 64 pc7/mco/beep i/o c x x x port c7 main clock-out beep signal 65 pd0/miso i/o c x ei5 x x port d0 spi master in / slave out data 66 pd1/mosi i/o c x x x port d1 spi master out / slave in data 67 pd2/sck i/o c x x x port d2 spi serial clock 68 pd3/ss i/o c x x x port d3 spi slave select (active low) 69 pd4/scli* i/o c x x x port d4 i2c clock** 70 pd5/sdai* i/o c x x x port d5 i2c data** 71 pd6 i/o c x ei5 x x port d6 72 pd7 i/o c x x x port d7 73 v ss_3 s digital ground voltage 74 v ss s ground voltage 75 v ss s ground voltage 76 v dd_3 s digital main supply voltage 77 to 84 com1 to com8 o c lcd lcd common (backplane) analog output 85 to 128 s1 to s44 o lcd lcd segment analog outputs pin n pin name type level port main func tion (after reset) alternate function pqfp128 input output input output float wpu int ana od pp
st72589bw, st72389bw 8/158 1.3 register & memory map as shown in the figure 3 , the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 128 bytes of register location, up to 1kbyte of ram, 60 bytes of lcd ram and up to 24kbytes of user pro- gram memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. figure 3. memory map table 2. interrupt vector map * available on st72589 version only. 0000h 512 bytes ram program memory interrupt & reset vectors hw registers 047fh 0080h short addressing ram (zero page) stack area 256 bytes 16-bit addressing ram 007fh 0480h 9fffh reserved 0100h 01ffh 027fh 0080h (see table 3 ) a000h ffdfh ffe0h ffffh (see table 1 ) lcd ram (60 bytes) 04bbh 04bch 0200h 00ffh 1024 bytes ram or 047fh 24 kbytes program memory 16 kbytes bfffh c000h vector address description remarks ffe0-ffe1h ffe2-ffe3h ffe4-ffe5h ffe6-ffe7h ffe8-ffe9h ffea-ffebh ffec-ffedh ffee-ffefh fff0-fff1h fff2-fff3h fff4-fff5h fff6-fff7h fff8-fff9h fffa-fffbh fffc-fffdh fffe-ffffh i2c interrupt vector* sci interrupt vector timer b interrupt vector timer a interrupt vector spi interrupt vector can interrupt vector* not used mcc interrupt vector external interrupt vector (ei5: port d) external interrupt vector (ei4: port c) external interrupt vector (ei3: port b) external interrupt vector (ei2: port a7..4) external interrupt vector (ei1: port a3..0) non maskable external interrupt vector (nmi) trap (software) interrupt vector reset vector internal interrupt external interrupt cpu interrupt
st72589bw, st72389bw 9/158 table 3. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 00h 00h r/w r/w r/w 0003h reserved area (1 byte) 0004h 0005h 0006h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 00h 00h r/w r/w r/w. 0007h reserved area (1 byte) 0008h 0009h 000ah port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 00h 00h r/w r/w r/w 000bh reserved area (1 byte) 000ch 000dh 000eh port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 00h 00h r/w r/w r/w 000fh to 001bh reserved area (13 bytes) 001ch 001dh 001eh 001fh itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0020h miscr1 miscellaneous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h watchdog wdgcr watchdog control register 7fh r/w 0025h reserved area (1 byte) 0026h mcc mccsr main clock control / status register 00h r/w 0027h reserved area (1 byte) 0028h 0029h 002ah 002bh 002ch 002dh 002eh i 2 c* i2ccr i2csr1 i2csr2 i2cccr i2coar1 i2coar2 i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c own address register 1 i 2 c own address register 2 i 2 c data register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w
st72589bw, st72389bw 10/158 002fh 0030h reserved area (2 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h miscr2 miscellaneous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00xx xxxx xxh 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w 0058h lcd lcdcr lcd control register 00h r/w 0059h reserved area (1 byte) address block register label register name reset status remarks
st72589bw, st72389bw 11/158 * note : available on st72589 version only. 005ah 005bh 005ch 005dh 005eh 005fh 0060h to 006fh can* canisr canicr cancsr canbrpr canbtr canpsr can interrupt status register can interrupt control register can control / status register can baud rate prescaler register can bit timing register can page selection register first address to last address of can page x 00h 00h 00h 00h 23h 00h -- r/w r/w r/w r/w r/w r/w see can description 0070h 0071h adc adcdr adccsr data register control/status register xxh 00h read only r/w 0072h 0073h reserved area (2 bytes) 0074h 0075h 0076h 0077h 0078h 0079h pwmbrm* pwm0 brm10 pwm1 pwm2 brm32 pwm3 10-bit pwm / brm registers 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks
st72589bw, st72389bw 12/158 1.4 memories and programming modes 1.4.1 eprom program memory the program memory of the otp and eprom de- vices can be programmed with eprom program- ming tools available from stmicroelectronics eprom erasure eprom devices are erased by exposure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo cur- rent. it is recommended that the eprom devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents.
st72589bw, st72389bw 13/158 2 central processing unit 2.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n low power halt and wait modes n priority maskable hardware interrupts n non-maskable software/hardware interrupts 2.3 cpu registers the 6 cpu registers shown in figure 4 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 4. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
st72589bw, st72389bw 14/158 central processing unit (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. its a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1
st72589bw, st72389bw 15/158 central processing unit (contd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 5 ). since the stack is 256 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 5 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 5. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
st72589bw, st72389bw 16/158 3 supply, reset and clock management this chapter describes the following generic fea- tures to guaranty the st7 correct operation. an overview is shown in figure 6 . n reset m anager n low consumption crystal oscillators n main clock controller (mcc) figure 6. clock and reset management overview f osc main clock controller (mcc) main oscillator f cpu from watchdog peripheral mcc interrupt mco osc1 osc2 reset f osc /2 reset
st72589bw, st72389bw 17/158 3.1 reset manager 3.1.1 introduction there are three sources of reset: C reset pin (external source) C power-on reset (internal source) C watchdog (internal source) the reset service routine vector is located at ad- dress fffeh-ffffh. figure 7. reset block diagram 3.1.2 external reset the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor (see figure 7 ). this pull-up has not a fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. a reset signal originating from an external source must have a duration of at least t pulse in order to be recognized. the reset sequence as- sociated to this reset source is shown in figure 8 . when the reset is generated by a internal source, during the two first phases of the r eset sequence, the device reset pin acts as an out- put that is pulled low. figure 8. external reset sequences f cpu counter reset r on v dd watchdog reset por internal reset reset run internal reset 4096 clock cycles fetch vector run reset pin external reset source t pulse watchdog reset delay
st72589bw, st72389bw 18/158 reset manager (contd) 3.1.3 internal watchdog reset the reset s equence generated by a internal watchdog counter underflow is reduced to 2 phas- es (see figure 9 ). figure 9. watchdog reset sequence 3.1.4 reset operation the duration of the reset condition, which is also reflected on the output pin, is fixed at 4096 internal cpu clock cycles. a reset signal originating from an external source must have a duration of at least 1.5 internal cpu clock cycles in order to be recog- nised. at the end of the power-on reset cycle, the mcu may be held in the reset condition by an ex- ternal reset signal. the reset pin may thus be used to ensure v dd has risen to a point where the mcu can operate correctly before the user pro- gram is run. following a reset event, or after exit- ing halt mode, a 4096 cpu clock cycle delay pe- riod is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the reset state. during the reset cycle, the device reset pin acts as an output that is pulsed low. in its high state, an internal pull-up resistor is connected to the reset pin. this resistor can be pulled low by external cir- cuitry to reset the device. 3.1.5 power-on reset this circuit detects the ramping up of v dd , and generates a pulse that is used to reset the applica- tion at v por supply voltage. power-on reset is designed exclusively to cope with power-up conditions, and should not be used in order to attempt to detect a drop in the power supply voltage. caution : to re-initialize the power-on reset, the power supply voltage must fall below v tn , prior to rise above v por . if this condition is not respected, on subsequent power-up the reset pulse may not be generated. an external reset pulse may be re- quired to correctly reactivate the circuit. reset run internal reset 4096 clock cycles fetch vector run reset pin external reset source watchdog reset watchdog underflow
st72589bw, st72389bw 19/158 3.2 low consumption oscillator the oscillator of the st72589 and st72389 devic- es is a crystal/ceramic resonator oscillator. its architecture is based on a constant current to min- imize the consumption. it can be used either with an external resonator or an external source. this oscillator allows a high accuracy to supply the clock for the st7 cpu and its internal peripherals. using a crystal/ceramic resonator the resonator and the load capacitances have to be connected as shown in figure 10 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. figure 10. main crystal/ceramic resonator using an external clock source in this mode, a square clock signal with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground (see figure 11 ). figure 11. main external clock source osc1 osc2 load capacitances st7 c l2 c l1 osc1 osc2 external st7 source
st72589bw, st72389bw 20/158 3.3 main clock controller (mcc) the mcc block supplies the clock for the st7 cpu and its internal peripherals. it allows to man- age the power saving modes such as the slow and active-halt modes. the whole functionali- ty is managed by the main clock control/status register (mccsr) and the miscellaneous regis- ter 2 (miscr2). the mcc block described in figure 12 consists of: C a programmable cpu clock prescaler C a time base counter with interrupt capability C a clock-out signal to supply external devices the prescaler allows to select the main clock fre- quency and is controlled with three bits of the mccsr: cp1, cp0 and sms. the counter allows to generate an interrupt based on a accurate real time clock. four different time bases depending directly on f osc are available. the whole functionality is controlled by four bits of the mccsr register: tb1, tb0, oie and oif. the clock-out capability allows to configure a ded- icated i/o port pin as an f osc /2 clock out to drive external devices. it is controlled by a bit in the miscr2 register: mco. figure 12. main clock controller (mcc) block diagram div 2, 4, 8, 16 mcc interrupt div 2 - - - tb1 tb0 oie oif cpu clock miscr2 programmable divider can to cpu and peripherals peripheral f osc f cpu mco port function alternate osc1 osc2 main oscillator - - - mco - 0 cp0 cp1 sms mccsr
st72589bw, st72389bw 21/158 main clock controller (contd) miscellaneous register 2 (miscr2) see description in miscellaneous register section. main clock control/status register (mccsr) read/write reset value: 0000 0000 (00h) bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc / 2 1: slow mode. f cpu is given by cp1, cp0 see low power consumption mode and mcc chapters for more details. bit 2:1 = cp1-cp0 cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 4 = reserved , always read as 0. bit 3:2 = tb1-tb0 time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disable 1: oscillator interrupt enable this interrupt allows to exit from active-halt mode. when this bit is set, calling the st7 soft- ware halt instruction accesses the active- halt power saving mode. bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the main oscillator has measured the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached warning : bres and bset instructions must not be used on the mccsr register to avoid unwant- ed clearing of oif bit. 70 sms cp1 cp0 0 tb1 tb0 oie oif f cpu in slow mode cp1 cp0 f osc / 4 0 0 f osc / 8 0 1 f osc / 16 1 0 f osc / 32 1 1 counter prescaler time base tb1 tb0 f osc =8mhz f osc =16mhz 32000 4ms 2ms 0 0 64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1
st72589bw, st72389bw 22/158 main clock controller (contd) table 4. main clock controller register map and reset values address (hex.) register label 76543210 0026h mccsr reset value sms 0 cp1 0 cp0 00 tb1 0 tb0 0 oie 0 oif 0
st72589bw, st72389bw 23/158 4 interrupts & power saving modes 4.1 interrupts 4.1.1 introduction the st7 enhanced interrupt management pro- vides the following features: n hardware interrupts n software interrupt (trap) n nested or concurrent interrupt management with flexible interrupt priority and level management: C up to 4 software programmable nesting levels C up to 16 interrupt vectors fixed by hardware C 3 non maskable events: nmi, reset, trap this interrupt management is based on: C bit 5 and bit 3 of the cpu cc register (i1:0), C interrupt software priority registers (isprx), C fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with the standard (not nest- ed) st7 interrupt controller. 4.1.2 interrupt masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see table 5 ). the process- ing flow is shown in figure 13 when an interrupt request has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the previous level will resume. table 5. interrupt software priority levels figure 13. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 iret restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset nmi pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt
st72589bw, st72389bw 24/158 interrupts (contd) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: C the highest software priority interrupt is serviced, C if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 14 describes this decision process. figure 14. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and nmi are non maskable and they can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, nmi, trap) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 13 ). after stacking the pc, x, a and cc registers (except for reset), the corres ponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. n nmi (non maskable hardware interrupt) this hardware interrupt occurs when a specific edge is detected on the dedicated nmi pin. its de- tailed specification is given in the miscellaneous register chapter. n trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart on figure 13 as an nmi. n reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. n external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the miscellaneous registers (miscrx). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. n peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the interrupt mapping table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced
st72589bw, st72389bw 25/158 interrupts (contd) 4.1.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit the halt modes (see column exit from halt in interrupt mapping table). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an inter- rupt with exit from halt mode capability and it is selected through the same decision process shown in figure 14 note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 4.1.4 concurrent and nested interrupt management the following figure 15 and figure 16 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 16 the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, nmi. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 15. concurrent interrupt management figure 16. nested interrupt management main it4 it2 it1 nmi it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 nmi it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 nmi main it0 it2 it1 it4 nmi it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes
st72589bw, st72389bw 26/158 interrupts (contd) 4.1.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see interrupt dedicated instruction set table). *note : nmi, trap and reset events are non maskable sources and can interrupt a level 3 pro- gram. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset values: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. C each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondence is shown in the following table. C each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. C level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and nmi vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the nmi can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits
st72589bw, st72389bw 27/158 interrupts (contd) table 6. dedicated interrupt instruction set note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. in order not to lose the current software priority level, the rim, sim, halt, wfi and pop cc instructions should never be used in an interrupt routine. table 7. interrupt mapping instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 nmi external non maskable interrupt miscr1 yes fffah-fffbh 1 ei1 external interrupt port a3..0 n/a fff8h-fff9h 2 ei2 external interrupt port a7..4 fff6h-fff7h 3 ei3 external interrupt port b6..0 fff4h-fff5h 4 ei4 external interrupt port c7..0 fff2h-fff3h 5 ei5 external interrupt port d7..0 fff0h-fff1h 6 mcc main oscillator time base interrupt mccsr ffeeh-ffefh 7 not used ffech-ffedh 8 can* can peripheral interrupts canisr ffeah-ffebh 9 spi spi peripheral interrupts spisr no ffe8h-ffe9h 10 timer a timer a peripheral interrupts tasr ffe6h-ffe7h 11 timer b timer b peripheral interrupts tbsr ffe4h-ffe5h 12 scip sci peripheral interrupts scisr ffe2h-ffe3h 13 i2c* i2c peripheral interrupts i2csrx ffe0h-ffe1h
st72589bw, st72389bw 28/158 interrupts (contd) table 8. nested interrupts register map and reset values address (hex.) register label 76543210 001ch ispr0 reset value ei3 ei2 ei1 nmi i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 001dh ispr1 reset value acc mcc ei5 ei4 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 001eh ispr2 reset value timer b timer a spi can i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 001fh ispr3 reset value1111 i2c sci i1_13 1 i0_13 1 i1_12 1 i0_12 1
st72589bw, st72389bw 29/158 4.2 power saving modes 4.2.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. figure 17. power saving mode consumption / transitions 4.2.2 halt modes the halt modes are the lowest power consump- tion modes of the mcu. they are entered by exe- cuting the st7 halt instruction (see figure 19 ). two different halt modes can be distinguished: C halt: main oscillator is turned off, C active-halt: only main oscillator is running. the decision to enter either in halt or active- halt mode is given by the main oscillator enable interrupt flag (oie bit in cross-mccsr register: see table 9 ). when entering halt modes, the i1 and i0 bits in the cc register are forced to level 0 (10) to ena- ble interrupts. the mcu can exit halt or active-halt modes on reception of either an external interrupt, an in- terrupt with exit from halt mode capability or a re- set (see table 2 ). a 4096 cpu clock cycles delay is performed before the cpu operation resumes (see figure 18 ). after the start up delay, the cpu resumes opera- tion by servicing the interrupt or by fetching the re- set vector which woke it up. table 9. halt modes selection figure 18. halt /active-halt modes timing overview power consumption wait slow run halt active-halt high low slow wait mccsr oie flag power saving mode entered when halt instruction is executed 0 halt (reset if watchdog enabled) 1 active-halt (no reset if watchdog enabled) halt or active-halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector
st72589bw, st72389bw 30/158 power saving modes (contd) standard halt mode in this mode the main oscillator is turned off caus- ing all internal processing to be stopped, including the operation of the on-chip peripherals. all periph- erals are not clocked except the ones which get their clock supply from another clock generator (such as an external oscillator). the halt instruction when executed while the watchdog system is enabled, generates a watch- dog reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabi- lize the oscillator. specific active-halt mode as soon as the interrupt capability of the main os- cillator is selected (oie bit set), the halt instruc- tion will make the device enter a specific active- halt power saving mode instead of the standard halt one. this mode consists of having only the main oscil- lator and its associated counter running to keep a wake-up time base. all other peripherals are not clocked except the ones which get their clock sup- ply from another clock generator (such as external oscillator). the safeguard against staying locked in this ac- tive-halt mode is insured by the oscillator inter- rupt. note: as soon as the interrupt capability of the os- cillators is selected (oie bit set), entering in ac- tive-halt mode while the watchdog is active does not generate a reset. this means that the device cannot to spend more than a defined delay in this power saving mode. figure 19. halt modes flow-chart halt instruction oscillator 1 0 cpu oscillator peripherals i1 and i0 bits on off 10 off notes: oie bit cpu oscillator peripherals i1 and i0 bits off off 10 off reset external* y n n y cpu oscillator peripherals on off off interrupt halt active-halt main fetch reset vector or service interrupt** 4096 clock cycles delay cpu oscillator peripherals on on on external interrupt or internal interrupts with exit from halt mode capability * ** before servicing an interrupt, the cc register is pushed on the stack. watchdog y n enable
st72589bw, st72389bw 31/158 power saving modes (contd) 4.2.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i1 and i0 bits of the cc register are forced to level 0 (10), to enable all interrupts. all other reg- isters and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branch- es to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 20 . figure 20. wait mode flow-chart wfi instruction reset interrupt y n n y cpu oscillator peripherals i1 and i0 bits on on 10 off if exit caused by a reset, a 4096 cpu clock cycle delay is inserted. cpu oscillator peripherals on off* off note: * the peripheral clock is stopped only when exit caused by reset and not by an interrupt. ** before servicing an interrupt, the cc register is pushed on the stack. fetch reset vector or service interrupt** cpu oscillator peripherals on on on
st72589bw, st72389bw 32/158 power saving modes (contd) 4.2.4 slow mode this mode has two targets: C to reduce power consumption by decreasing the internal clock in the device, C to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the main oscillator csr register: the sms bit which enables or disables slow mode and two cpx bits which se- lect the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals (except can, see note) are clocked at this lower frequency. note: before entering slow mode and in order to guarantee low power operation, the can peripher- al must be placed by software in standby mode. figure 21. slow mode: timing diagram for internal cpu clock transitions 00 01 0 1 sms cp1:0 f cpu f osc /8 f osc /4 new frequency request new frequency active when osc/4 & osc/8 = 0 normal mode request normal mode active (osc/4, osc/8 stopped) main osillator csr
st72589bw, st72389bw 33/158 5 i/o ports 5.1 introduction the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C external interrupt generation C alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.2 functional description each port has 2 main registers: C data register (dr) C data direction register (ddr) and one optional register: C option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 1 5.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. do not use read/modify/write instructions (bset or bres) to modify the dr register external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically nanded. for this reason if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see figure 2 ). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 5.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 5.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pull open-drain 0v ss vss 1v dd floating
st72589bw, st72389bw 34/158 i/o ports (contd) figure 22. i/o port general block diagram table 10. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up configuration p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access
st72589bw, st72389bw 35/158 i/o ports (contd) table 11. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) configuration pad v dd r pu external interrupt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register configuration alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports
st72589bw, st72389bw 36/158 i/o ports (contd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 5.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 2 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 23. interrupt i/o port state transitions the i/o port register configurations are summa- rized as follows. standard interrupt ports pa7:0, pb6:0, pc7:0, pd7:6, pd3:0 open drain ports pd5:4 dedicated configurations table 12. port configuration mode ddr or floating input 0 0 floating interrupt 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain output 1 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:pa0 floating floating interrupt open drain push-pull port b pb6:pb0 port c pc7:pc0 port d pd3:pd0 pd5:pd4 floating open-drain pd7:pd6 floating floating interrupt open drain push-pull
st72589bw, st72389bw 37/158 i/o ports (contd) 5.3.1 register description data register (dr) port x data register pxdr with x = a, b, c or d. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b, c or d. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, b, c or d. read/write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the floating interrupt capability or the basic floating configuration is selected, in output mode if the push-pull or open drain configuration is select- ed. each bit is set and cleared by software. input mode: 0: floating input 1: floating input with interrupt output mode: 0: output open drain (with p-buffer unactivated) 1: output push-pull 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0
st72589bw, st72389bw 38/158 i/o ports (contd) table 13. i/o port register map and reset values address (hex.) register label 76543210 reset value of all io port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0004h pbdr msb lsb 0005h pbddr 0006h pbor 0008h pcdr msb lsb 0009h pcddr 000ah pcor 000ch pddr msb lsb 000dh pdddr 000eh pdor
st72589bw, st72389bw 39/158 6 miscellaneous registers the miscellaneous registers allow control over several features such as external interrupts or the i/o alternate functions. 6.1 i/o port interrupt sensitivity description the external interrupt sensitivity is controlled by the isxx bits of the miscellaneous registers ( figure 24 ). this control allows to have 2 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level to guaranty the functionality, a modification of the sensitivity in the miscr registers can be done only when the i1 and i0 bits of the cc register are both set to 1 (level 3). see i/o port register and miscellaneous register descriptions for more de- tails on the programming. 6.2 i/o port alternate functions the miscr registers allow to manage three i/o port miscellaneous alternate functions: n a beep signal output on pc7 (with three selectable audio frequencies) n a nmi management on a dedicated pin n a spi ss pin internal control to use the pd3 i/o port function while the spi is active. these functions are described in details in the section 6.3 miscellaneous registers description . figure 24. external interrupt sources vs miscr ei1 interrupt source ei3 interrupt source is10 is11 miscr1 sensitivity control pa3 pa2 pa1 pa0 sources pb6 pb0 sources pd7 pd0 sources ei5 interrupt source ei2 interrupt source ei4 interrupt source is20 is21 miscr1 sensitivity control pa7 pa6 pa5 pa4 sources pc7 pc0 sources
st72589bw, st72389bw 40/158 miscellaneous registers (contd) 6.3 miscellaneous registers description miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bit 7:6 = is11-is10 ei1,3, 5 sensitivity the selection issued from is11,is10 combination is applied to the following external interrupts: ei1 (port a3..0) ei3 (port b) and ei5 (port d). these 2 bits can be written only when the current interrupt software priority in the cc (condition code) register is set to level 3 (i1:0=11). bit 5:4 = is21-is20 ei2,4 sensitivity the selection issued from is21,is20 combination is applied to the following external interrupts: ei2 (port a7..4) and ei4 (port c). the functional description is equal to the is1x one. bit 3:2 = reserved , always read as 0. bit 1 = nmis nmi sensitivity this bit allows to toggle the nmi edge sensitivity. it can be set and cleared by software only when nmie bit is cleared. 0: falling edge 1: rising edge bit 0 = nmie nmi enable this bit allows to enable or disable the nmi capa- bility on the dedicated pin. it is set and cleared by software. 0: nmi disable 1: nmi enable miscellaneous register 2 (miscr2) read/write reset value: 0000 0000 (00h) bit 7 = reserved. bit 6:4 = mco main clock-out control bc1-bc0 beep control these 3 bits select the pc7 pin configuration. they are set and cleared by software. note : the clock out and beep capabilities are not available in halt modes. bit 3:2 = reserved , always read as 0. bit 1 = ssm ss mode selection it is set and cleared by software. 0: normal mode - ss uses information coming from the ss pin of the spi. 1: i/o mode, the spi uses the information stored into bit ssi. bit 0 = ssi ss internal mode this bit replaces pin ss of the spi when bit ssm is set to 1. (see spi description). it is set and cleared by software. 70 is11 is10 is21 is20 0 0 nmis nmie isx1 isx0 external interrupt sensitivity 0 0 falling edge and low level 0 1 falling edge only 1 0 rising edge only 1 1 rising and falling edge 70 0 mco bc1 bc0 0 0 ssm ssi mco bc1 bc0 pc7 configuration 0 0 0 standard i/o 100 f osc /2 clock out x 0 1 ~2-khz output beep signal w/ f osc =16mhz ~50% duty cycle x 1 0 ~1-khz x 1 1 ~500-hz
st72589bw, st72389bw 41/158 miscellaneous registers (contd) table 14. miscellaneous register map and reset values address (hex.) register label 76543210 0020h miscr1 reset value is11 0 is10 0 is21 0 is20 000 nmis 0 nmi 0 0040h miscr2 reset value 0 mco 0 bc1 0 bc0 000 ssm 0 ssi 0
st72589bw, st72389bw 42/158 7 on-chip peripherals 7.1 lcd driver 7.1.1 introduction the lcd driver controls up to 60 segments and 8 backplanes to drive up to 60x8 (480) or 60x4(240) lcd segments. two programmable display modes (1/4 and 1/8 duty cycle) with 4 lcd drive frequencies can be selected by software. the parameters to display are stored in a 60-byte lcd dual port ram. four different main oscillator clocks can be select- ed as clock for the peripheral. C 8, 4, 2, 1 mhz f cpu software selectable. the peripheral can be switched off by software to reduce the power consumption while it is not used. figure 25. lcd frequency generator block diagram 7.1.2 voltage references the display voltage levels are supplied by an ex- ternal resistor chain as shown in figure 26 this lcd driver needs 5 external voltage references through 5 pins (glcd, 1/4vlcd, 1/2vlcd, 3/4vlcd, vlcd). the resistors used must have good tolerance matching within 1% to avoid dc voltage levels on the liquid crystal device. dc levels trigger elec- trode reactions in the liquid crystal cell, causing a rapid deterioration of the display quality. note : to avoid damaging the device, vlcd supply voltages must always be supplied with more than v dd or they have to be left unconnected. figure 26. lcd external supply network clock divider f fr f lcdin ? 16khz f cpu f lcd ? 0.5...2khz div 8,16,24,32 dcs 0 cd1 cd0 lcde 0 fs1 fs0 cr backplane mux main oscillator (seg, com) r lcd 1 vlcd external v lcd 3/4vlcd 1/2vlcd 1/4vlcd glcd r lcd 2 r lcd 3 r lcd 4 c lcd 1 c lcd 2 c lcd 3
st72589bw, st72389bw 43/158 lcd driver (contd) 7.1.3 segment and common output signals each dot of the lcd dot matrix panel is turned on when the differential voltage between the segment signal and the common signal increases over a certain threshold, it is turned off when the voltage is below the threshold voltage. the common sig- nals determine the select timing within a frame cy- cle (see figure 27 ). the common signals have similar waveforms to the segments, but different phases. figure 27. waveforms on lcd outputs each common signal shows a high signal ampli- tude (vlcd-vss) only at the corresponding sec- tion of a frame time. at the other sections of the frame, the signal amplitude is low (3/4vlcd-1/ 4vlcd). a dot can be turned-on only at phases with high signal amplitude. in 1/8 duty cycle mode, one frame is divided into 8 sections, and each section is divided into two phases, phase 0 and 1. in 1/4 duty cycle mode, the number of sections is reduced to 4. this means the waveform pattern repeats faster in 1/4 duty cycle mode than 1/8 mode and the average voltage and the on/off duty cycle on a selected pin is higher than in 1/8 mode. this results in a bet- ter contrast of the display. note: the lcd must be disabled before entering halt mode or active halt mode. figure 28. lcd outputs with 1/8 multiplex v lcd 3/4 1/2 1/4 gnd 0101 common selected v lcd 3/4 1/2 1/4 gnd 0101 common off v lcd 3/4 1/2 1/4 gnd 0101 segment selected v lcd 3/4 1/2 1/4 gnd 0101 segment off v lcd 3/4 1/2 1/4 gnd com8 v lcd 3/4 1/2 1/4 gnd com7 v lcd 3/4 1/2 1/4 gnd seg1 v lcd 3/4 1/2 1/4 gnd seg2 8 76 5 218 one frame period com8 com7 com6 com5 com4 com3 com2 com1 seg1 seg2 seg3 seg4 seg5 seg6 01010101 010101
st72589bw, st72389bw 44/158 lcd driver (contd) 7.1.4 register description lcd control register (cr) read/write reset value: 0000 0000 (00h) bit 7 = dcs duty cycle selection this bit is set and cleared by software. 0: 1/4 duty cycle selected 1: 1/8 duty cycle selected bit 6 = reserved, always read as 0. bit 5:4 = cd1,cd0 clock divider these bits allow to tune the f lcdin frequency to ~16khz based on the selected f cpu . these bits are set and cleared by software. bit 3 = lcde lcd enable this bit is set and cleared by software. 0: lcd disable 1: lcd enable while the lcd is disabled (lcde bit cleared), glcd is applied to all segment and common pins. bit 2 = reserved , must be kept cleared. bit 1:0 = fs1,fs0 f fr frame frequency selection these two bits allow to select the lcd frame fre- quency based on the f lcdin frequency and the se- lected duty cycle. these bits are set and cleared by software. the following table gives the possible lcd seg- ment frequency ( f lcd ) and lcd frame frequency ( f fr ) according to the selected duty cycle. with f lcdin =15625hz (main oscillator) 70 dcs 0 cd1 cd0 lcde 0 fs1 fs0 f lcdin f cpu divider cd1 cd0 15625hz 8-mhz 1/512 0 0 4-mhz 1/256 1 1 2-mhz 1/128 1 0 1-mhz 1/64 0 1 f lcdin ratio f lcd f fr fs1 fs0 1/4 d.c. 1/8 d.c. 1/8 1953-hz 488-hz 244-hz 0 0 1/16 977-hz 244-hz 122-hz 0 1 1/24 651-hz 163-hz 81-hz 1 0 1/32 488-hz 122-hz 61-hz 1 1
st72589bw, st72389bw 45/158 lcd driver (contd) lcd ram description the lcd ram is located in the data space in one page of 60 bytes. each bit of the lcd ram is mapped to one dot of the lcd matrix. if a bit is set, the corresponding lcd dot is switched on, else the dot is switched off. after reset, the lcd ram is not initialized and con- tains arbitrary information. the bit position of the selected bit in the lcd ram byte gives the common data. the segment data is giv- en by the lcd ram relative address. table 15. lcd driver register map and reset values lcd ram bit position 7 6 5 4 3 2 1 0 lcd common com8 com7 com6 com5 com4 com3 com2 com1 lcd ram relative address 00h 01h 02h ................... 39h 3ah 3bh lcd segment s1 s2 s3 s58 s59 s60 address (hex.) register label 76543210 0058h lcdcr reset value dcs 00 cd1 0 cd0 0 lcde 00 fs1 0 fs0 0 0480h to 04bbh lcdram reset value seg x com8 x seg x com7 x seg x com6 x seg x com5 x seg x com4 x seg x com3 x seg x com2 x seg x com1 x
st72589bw, st72389bw 46/158 7.2 watchdog timer (wdg) 7.2.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 7.2.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero figure 29. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 12288 t1 t2 t3 t4 t5
st72589bw, st72389bw 47/158 watchdog timer (contd) 7.2.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 16 . watchdog timing (fcpu = 8 mhz) ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 16. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 7.2.4 low power modes 7.2.5 interrupts none. 7.2.6 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 mode description wait no effect on watchdog. halt immediate reset generation as soon as the halt instruction is executed if the watchdog is activated (wdga bit is set). 70 wdga t6 t5 t4 t3 t2 t1 t0
st72589bw, st72389bw 48/158 watchdog timer (condt) table 17. watchdog timer register map and reset values address (hex.) register label 76543210 0024h wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
st72589bw, st72389bw 49/158 7.3 16-bit timer 7.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture ) or generating up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 7.3.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with: C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with: C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 30 . *note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be 1. 7.3.3 functional description 7.3.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register (sr). (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 18 clock control bits . the value in the counter register re- peats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
st72589bw, st72389bw 50/158 16-bit timer (contd) figure 30. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note)
st72589bw, st72389bw 51/158 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accessing the aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 7.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
st72589bw, st72389bw 52/158 16-bit timer (contd) figure 31. counter timing diagram, internal clock divided by 2 figure 32. counter timing diagram, internal clock divided by 4 figure 33. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high. when it is low, the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st72589bw, st72389bw 53/158 16-bit timer (contd) 7.3.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition is detected by the icap i pin (see figure 5). the ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function, select the fol- lowing in the cr2 register: C select the timer clock (cc[1:0]) (see table 18 clock control bits ). C select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). when an input capture occurs: C the icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 35 ). C a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, the transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 function can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with an interrupt in order to measure events that exceed the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr
st72589bw, st72389bw 54/158 16-bit timer (contd) figure 34. input capture block diagram figure 35. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge.
st72589bw, st72389bw 55/158 16-bit timer (contd) 7.3.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the oc i e bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 18 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 18 clock control bits ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext
st72589bw, st72389bw 56/158 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 37 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 38 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in either one-pulse mode or pwm mode. figure 36. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1
st72589bw, st72389bw 57/158 16-bit timer (contd) figure 37. output compare timing diagram, f timer =f cpu /2 figure 38. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i )
st72589bw, st72389bw 58/158 16-bit timer (contd) 7.3.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 18 clock control bits ). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and the olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 18 clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin (see figure 39 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the olvl2 level is dedi- cated to one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st72589bw, st72389bw 59/158 16-bit timer (contd) figure 39. one pulse mode timing example figure 40. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2
st72589bw, st72389bw 60/158 16-bit timer (contd) 7.3.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functions cannot be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if olvl1=0 and olvl2=1, using the formula in the oppo- site column. 3. select the following in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. C set the pwm bit. C select the timer clock (cc[1:0]) (see table 18 clock control bits ). if olvl1=1 and olvl2=0, the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 18 clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 40 ) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode, therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected from the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset after each period and icf1 can also generate an interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
st72589bw, st72389bw 61/158 16-bit timer (contd) 7.3.4 low power modes 7.3.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 7.3.6 summary of timer modes 1) see note 4 in section 7.3.3.5 one pulse mode 2) see note 5 in section 7.3.3.5 one pulse mode 3) see note 4 in section 7.3.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with exit from halt mode capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no
st72589bw, st72389bw 62/158 16-bit timer (contd) 7.3.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1
st72589bw, st72389bw 63/158 16-bit timer (contd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 18. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin (extclk) will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11
st72589bw, st72389bw 64/158 16-bit timer (contd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter has rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter matches the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72589bw, st72389bw 65/158 16-bit timer (contd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72589bw, st72389bw 66/158 16-bit timer (contd) table 19. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb -
st72589bw, st72389bw 67/158 7.4 pwm/brm generator (dac) 7.4.1 introduction this pwm/brm peripheral includes a 6-bit pulse width modulator (pwm) and a 4-bit binary rate multiplier (brm) generator. it allows the digital to analog conversion (dac) when used with external filtering. note: the number of pwm and brm channels available depends on the device. refer to the de- vice pin description and register map. 7.4.2 main features n fixed frequency: f cpu /64 n resolution: t cpu n steps of v dd /2 10 (5mv if v dd =5v) 7.4.3 functional description the 10 bits of the 10-bit pwm/brm are distributed as 6 pwm bits and 4 brm bits. the generator con- sists of a 10-bit counter (common for all channels), a comparator and the pwm/brm generation logic. pwm generation the counter increments continuously, clocked at internal cpu clock. whenever the 6 least signifi- cant bits of the counter (defined as the pwm coun- ter) overflow, the output level for all active chan- nels is set. the state of the pwm counter is continuously compared to the pwm binary weight for each channel, as defined in the relevant pwm register, and when a match occurs the output level for that channel is reset. this pulse width modulated signal must be fil- tered, using an external rc network placed as close as possible to the associated pin. this pro- vides an analog voltage proportional to the aver- age charge passed to the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc net- work should be selected for the filtering level re- quired for control of the system variable. each output may individually have its polarity in- verted by software, and can also be used as a log- ical output. figure 41. pwm generation counter 63 compare value overflow overflow overflow 000 t pwm output t t cpu x 64
st72589bw, st72389bw 68/158 pwm/brm generator (contd) pwm/brm outputs the pwm/brm outputs are assigned to dedicated pins. in these pins, the pwm/brm outputs are connect- ed to a serial resistor which must be taken into ac- count to calculate the rc filter (see figure 42 ). in any case, the rc filter time must be higher than t cpu x64. figure 42. typical pwm output filter table 20. 6-bit pwm ripple after filtering with rc filter (r=1k w ), f cpu = 8 mhz v dd = 5v pwm duty cycle 50% r=r int +r ext (rext is optional). note : after a reset these pins are tied low by de- fault and are not in a high impedance state. figure 43. pwm simplified voltage output after filtering 1k (max) c ext output voltage stage r int output r ext cext (f) v ripple (mv) 0.128 78 1.28 7.8 12.8 0.78 v dd 0v 0v dd v v ripple (mv) v outavg "charge" "discharge" "charge" "discharge" 0v v v 0v outavg v (mv) ripple v "charge" "discharge" "charge" "discharge" pwmout dd dd pwmout output voltage output voltage
st72589bw, st72389bw 69/158 pwm/brm generator (contd) brm generation the brm bits allow the addition of a pulse to wid- en a standard pwm pulse for specific pwm cy- cles. this has the effect of fine-tuning the pwm duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. the incremental pulses (with duration of t cpu ) are added to the beginning of the original pwm pulse. the pwm intervals which are added to are speci- fied in the 4-bit brm register and are encoded as shown in the following table. the brm values shown may be combined together to provide a summation of the incremental pulse intervals specified. the pulse increment corresponds to the pwm res- olution. for example,if C data 18h is written to the pwm register C data 06h (00000110b) is written to the brm reg- ister C with a 8mhz internal clock (125ns resolution) then 3.0 m s-long pulse will be output at 8 m s inter- vals, except for cycles numbered 2,4,6,10,12,14, where the pulse is broadened to 3.125 m s. note. if 00h is written to both pwm and brm reg- isters, the generator output will remain at 0. con- versely, if both registers hold data 3fh and 0fh, respectively, the output will remain at 1 for all in- tervals 1 to 15, but it will return to zero at interval 0 for an amount of time corresponding to the pwm resolution (t cpu ). an output can be set to a continuous 1 level by clearing the pwm and brm values and setting pol = 1 (inverted polarity) in the pwm register. this allows a pwm/brm channel to be used as an additional i/o pin if the dac function is not re- quired. table 21. bit brm added pulse intervals (interval #0 not selected). figure 44. brm pulse addition (pwm > 0) brm 4 - bit data incremental pulse intervals 0000 none 0001 i = 8 0010 i = 4,12 0100 i = 2,6,10,14 1000 i = 1,3,5,7,9,11,13,15 t cpu x 64 t cpu x 64 t cpu x 64 t cpu x 64 increment m = 1 m = 0 m = 2 t cpu x 64 m = 15
st72589bw, st72389bw 70/158 pwm/brm generator (contd) figure 45. simplified filtered voltage output schematic with brm added figure 46. graphical representation of 4-bit brm added pulse positions vdd pwmout 0v vdd output voltage 0v brm = 1 brm = 0 t cpu brm extended pulse = = 0100 bit2=1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwm pulse number (0-15) brm value 0001 bit0=1 0010 bit1=1 1000 bit3=1 examples 0110 1111
st72589bw, st72389bw 71/158 pwm/brm generator (contd) figure 47. precision for pwm/brm tuning for vouteff (after filtering) 7.4.4 register description on a channel basis, the 10 bits are separated into two data registers: note: the number of pwm and brm channels available depends on the device. refer to the de- vice pin description and register map. pulse binary weight registers (pwmi) read / write reset value 1000 0000 (80h) bit 7 = reserved (forced by hardware to 1) bit 6 = pol polarity bit for channel i. 0: the channel i outputs a 1 level during the bina- ry pulse and a 0 level after. 1: the channel i outputs a 0 level during the bina- ry pulse and a 1 level after. bit 5:0 = p[5:0] pwm pulse binary weight for channel i. this register contains the binary value of the pulse. brm registers read / write reset value: 0000 0000 (00h) these registers define the intervals where an in- cremental pulse is added to the beginning of the original pwm pulse. two brm channel values share the same register. bit 7:4 = b[7:4] brm bits (channel i+1). bit 3:0 = b[3:0] brm bits (channel i) note: from the programmer's point of view, the pwm and brm registers can be regarded as be- ing combined to give one data value. for example : effective (with external rc filtering) dac value 70 1 pol p5 p4 p3 p2 p1 p0 70 b7 b6 b5 b4 b3 b2 b1 b0 1polpppppp+bbbb 1polppppppbbbb
st72589bw, st72389bw 72/158 pwm/brm generator (condt) table 22. pwm register map and reset values address (hex.) register name 76543210 74 pwm0 reset value 1 pol 0 p5 0 p4 0 p3 0 p2 0 p1 0 p0 0 75 brm10 reset value b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 76 pwm1 reset value 1 pol 0 p5 0 p4 0 p3 0 p2 0 p1 0 p0 0 77 pwm2 reset value 1 pol 0 p5 0 p4 0 p3 0 p2 0 p1 0 p0 0 78 brm32 reset value b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 79 pwm3 reset value 1 pol 0 p5 0 p4 0 p3 0 p2 0 p1 0 p0 0
st72589bw, st72389bw 73/158 7.5 serial peripheral interface (spi) 7.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 7.5.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = f cpu /4. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 7.5.3 general description the spi is connected to external devices through 4 alternate pins: C miso: master in slave out pin C mosi: master out slave in pin C sck: serial clock pin Css : slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 48 . the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 51 ) but master and slave must be programmed with the same timing mode. figure 48. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit
st72589bw, st72389bw 74/158 serial peripheral interface (contd) figure 49. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - -- -- it request master control
st72589bw, st72389bw 75/158 serial peripheral interface (contd) 7.5.4 functional description figure 48 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: C a control register (cr) C a status register (sr) C a data register (dr) refer to the cr, sr and dr registers in section 7.5.7 for the bit definitions. 7.5.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure C select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). C select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 51 ). Cthe ss pin must be connected to a high level signal during the complete byte transmit se- quence. C the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a read to the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read.
st72589bw, st72389bw 76/158 serial peripheral interface (contd) 7.5.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure C for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 51 . Cthe ss pin must be connected to a low level signal during the complete byte transmit se- quence. C clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2.a read to the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 7.5.4.6 ). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 7.5.4.4 ).
st72589bw, st72389bw 77/158 serial peripheral interface (contd) 7.5.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 51 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 50 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 50 ). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 50. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a
st72589bw, st72389bw 78/158 serial peripheral interface (contd) figure 51. data clock timing diagram cpol = 1) cpol = 0) miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit sclk (with sclk (with
st72589bw, st72389bw 79/158 serial peripheral interface (contd) 7.5.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 52 ). figure 52. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing to the dr register instead of reading in it does not reset the wcol bit read sr or then then then
st72589bw, st72389bw 80/158 serial peripheral interface (contd) 7.5.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: C the modf bit is set and an spi interrupt is generated if the spie bit is set. C the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 7.5.4.6 overrun condition an overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al.
st72589bw, st72389bw 81/158 serial peripheral interface (contd) 7.5.4.7 single master and multimaster configurations there are two types of spi systems: C single master system C multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 53 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 53. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
st72589bw, st72389bw 82/158 serial peripheral interface (contd) 7.5.5 low power modes 7.5.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no
st72589bw, st72389bw 83/158 serial peripheral interface (contd) 7.5.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 7.5.4.5 master mode fault ). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 23 . 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 7.5.4.5 master mode fault ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 23. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1
st72589bw, st72389bw 84/158 serial peripheral interface (contd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 52 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 7.5.4.5 master mode fault ). an spi interrupt can be gen- erated if spie=1 in the cr register. this bit is cleared by a software sequence (an access to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a read to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 49 ). 70 spifwcol-modf---- 70 d7 d6 d5 d4 d3 d2 d1 d0
st72589bw, st72389bw 85/158 serial peripheral interface (contd) table 24. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spisr reset value spif 0 wcol 00 modf 00000
st72589bw, st72389bw 86/158 7.6 serial communications interface (sci) 7.6.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 7.6.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 250k baud using conventional baud rate generator and up to 500k baud using the extended baud rate generator. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: C address bit (msb) C idle line n muting function for multiprocessor configurations n lin compatible (if mcu clock frequency tolerance 2%) n separate enable bits for transmitter and receiver n three error detection flags: C overrun error C noise error C frame error n five interrupt sources with flags: C transmit data register empty C transmission complete C receive data register full C idle line received C overrun error detected 7.6.3 general description the interface is externally connected to another device by two pins (see figure 2.): C tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. C rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: C an idle line prior to transmission or reception C a start bit C a data word (8 or 9 bits) least significant bit first C a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: C a conventional type for commonly-used baud rates, C an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. 7.6.4 lin protocol support for lin applications where resynchronization is not required (application clock tolerance less than or equal to 2%) the lin protocol can be efficiently implemented with this standard sci.
st72589bw, st72389bw 87/158 serial communications interface (contd) figure 54. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe - sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie cr2
st72589bw, st72389bw 88/158 serial communications interface (contd) 7.6.5 functional description the block diagram of the serial control interface, is shown in figure 1.. it contains 6 dedicated reg- isters: C two control registers (cr1 & cr2) C a status register (sr) C a baud rate register (brr) C an extended prescaler receiver register (erpr) C an extended prescaler transmitter register (etpr) refer to the register descriptions in section 0.1.8 for the definitions of each bit. 7.6.5.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 1.). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of 1s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving 0s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra 1 bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 55. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra 1 data frame break frame start bit extra 1 data frame next data frame next data frame
st72589bw, st72389bw 89/158 serial communications interface (contd) 7.6.5.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 1.). procedure C select the m bit to define the word length. C select the desired baud rate using the brr and the etpr registers. C set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. C access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates: C the tdr register is empty. C the data transfer is beginning. C the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register and which is copied in the shift regis- ter at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit l oads the shift register with a break character. the break frame length depends on the m bit (see figure 2.). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the dr.
st72589bw, st72389bw 90/158 serial communications interface (contd) 7.6.5.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, dr register consists in a buffer (rdr) between the in- ternal bus and the received shift register (see fig- ure 1.). procedure C select the m bit to define the word length. C select the desired baud rate using the brr and the erpr registers. C set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: C the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. C an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. C the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: C the or bit is set. C the rdr content will not be lost. C the shift register will be overwritten. C an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: C the nf is set at the rising edge of the rdrf bit. C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: C the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. C a break is received. when the framing error is detected: C the fe bit is set by hardware C data is transferred from the shift register to the dr register. C no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation.
st72589bw, st72389bw 91/158 serial communications interface (contd) figure 56. sci baud rate and extended prescaler block diagram transmitter receiver etpr erpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register
st72589bw, st72389bw 92/158 serial communications interface (contd) 7.6.5.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all this bits are in the brr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 baud. caution: the baud rate register (scibrr) must not be written to (changed or refreshed) while the transmitter or the receiver is enabled. 7.6.5.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 3.. the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the erpr or the etpr register. note: the extended prescaler is activated by set- ting the etpr or erpr register to a value other than zero. the baud rates are calculated as fol- lows: with: etpr = 1,..,255 (see etpr register) erpr = 1,.. 255 (see erpr register) 7.6.5.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: C by idle line detection if the wake bit is reset, C by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a 1 as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu tx = 16 * etpr f cpu rx = 16 * erpr f cpu
st72589bw, st72389bw 93/158 serial communications interface (contd) 7.6.6 low power modes 7.6.7 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie yes no overrrun error detected or yes no idle line detected idle ilie yes no
st72589bw, st72389bw 94/158 serial communications interface (contd) 7.6.8 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by a software sequence (an ac- cess to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software se- quence (an access to the sr register followed by a read to the dr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = unused. 70 tdre tc rdrf idle or nf fe -
st72589bw, st72389bw 95/158 serial communications interface (contd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a 0 pulse on the te bit (0 followed by 1) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to 1 and then to 0, the transmitter will send a br eak word at the end of the current word. 70 r8 t8 - m wake - - - 70 tie tcie rie ilie te re rwu sbk
st72589bw, st72389bw 96/158 serial communications interface (contd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 1.). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 1.). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the etpr dividing factor. bit 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the erpr dividing factor. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividing factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1
st72589bw, st72389bw 97/158 serial communications interface (contd) extended receive prescaler division register (erpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bit 7:1 = erpr[7:0] 8-bit extended receive pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3.) is divided by the binary factor set in the erpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (etpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bit 7:1 = etpr[7:0] 8-bit extended transmit pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 3.) is divided by the binary factor set in the etpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0
st72589bw, st72389bw 98/158 serial communications interface (contd) table 25. sci register map and reset values address (hex.) register label 76543210 50 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 00 51 scidr reset value msb xxxxxxx lsb x 52 scibrr reset value scp1 0 scp0 0 sct2 x sct1 x sct0 x scr2 x scr1 x scr0 x 53 scicr1 reset value r8 x t8 x0 m x wake x000 54 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 55 scipbrr reset value msb 0000000 lsb 0 57 scipbrt reset value msb 0000000 lsb 0
st72589bw, st72389bw 99/158 7.7 i 2 c bus interface (i2c) 7.7.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i 2 c mode (400khz). 7.7.2 main features n parallel-bus/i 2 c protocol converter n multi-master capability n 7-bit/10-bit addressing n transmitter/receiver flag n end-of-byte transmission flag n transfer problem detection i 2 c master features: n clock generation n i 2 c bus busy flag n arbitration lost flag n end of byte transmission flag n transmitter/receiver flag n start bit detection flag n start and stop generation i 2 c slave features: n stop bit detection n i 2 c bus busy flag n detection of misplaced start or stop condition n programmable i 2 c address detection n transfer problem detection n end-of-byte transmission flag n transmitter/receiver flag 7.7.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. mode selection the interface can operate in the four following modes: C slave transmitter/receiver C master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master ca- pability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recog- nising its own address (7 or 10-bit), and the gen- eral call address. the general call address de- tection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte(s) following the start con- dition contain the address (one in 7-bit mode, two in 10-bit mode). the address is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 57 . figure 57. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b
st72589bw, st72389bw 100/158 i 2 c bus interface (contd) acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call ad- dress can be selected by software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i 2 c (100- 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 58. i 2 c interface block diagram data register (dr) data shift register comparator own address register 1 (oar1) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai own address register 2 (oar2)
st72589bw, st72389bw 101/158 i 2 c bus interface (contd) 7.7.4 functional description refer to the cr, sr1 and sr2 registers in section 7.7.7 . for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. first the interface frequency must be configured using the fri bits in the oar2 register. 7.7.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). note: in 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and the two most significant bits of the address. header matched (10-bit mode only): the interface generates an acknowledge pulse if the ack bit is set. address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: C acknowledge pulse if the ack bit is set. C evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 59 transfer sequencing ev1). next, in 7-bit mode read the dr register to deter- mine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. in 10-bit mode, after receiving the address se- quence the slave is always in receive mode. it will enter transmit mode on receiving a repeated start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1) . slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the inter- nal shift register. after each byte the interface gen- erates in sequence: C acknowledge pulse if the ack bit is set C evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 59 transfer se- quencing ev2). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 59 transfer sequencing ev3). when the acknowledge pulse is received: C the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: C evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 reg- ister (see figure 59 transfer sequencing ev4). error cases C berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. note : in both cases, scl line is not held low; how- ever, sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software.
st72589bw, st72389bw 102/158 i 2 c bus interface (contd) how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. 7.7.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condi- tion. once the start condition is sent: C the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address, holding the scl line low (see figure 59 transfer sequencing ev5). slave address transmission then the slave address is sent to the sda line via the internal shift register. in 7-bit addressing mode, one address byte is sent. in 10-bit addressing mode, sending the first byte including the header sequence causes the follow- ing event: C the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register, holding the scl line low (see figure 59 transfer se- quencing ev9). then the second address byte is sent by the inter- face. after completion of this transfer (and acknowledge from the slave if the ack bit is set): C the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fig- ure 59 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. note: in 10-bit addressing mode, to switch the master to receiver mode, software must generate a repeated start condition and resend the header sequence with the least significant bit set (11110xx1). master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr reg- ister via the internal shift register. after each byte the interface generates in sequence: C acknowledge pulse if if the ack bit is set C evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister followed by a read of the dr register, holding the scl line low (see figure 59 transfer se- quencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte.
st72589bw, st72389bw 103/158 i 2 c bus interface (contd) master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 59 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: C evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gener- ate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases C berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. C arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then neces- sary to release both lines by software.
st72589bw, st72389bw 104/158 i 2 c bus interface (contd) figure 59. transfer sequencing legend: s=start, s r = repeated start, p=stop, a=acknowledge, na=non-acknowledge, evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by reading sr1 register. btf is cleared by releasing the lines (stop=1, stop=0) or by writing dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev6: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev9: evf=1, add10=1, cleared by reading sr1 register followed by writing dr register. 7-bit slave receiver: 7-bit slave transmitter: 7-bit master receiver: 7-bit master transmitter: 10-bit slave receiver: 10-bit slave transmitter: 10-bit master transmitter 10-bit master receiver: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a ..... datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a ..... datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 s header a address a data1 a ..... datan a p ev1 ev2 ev2 ev4 s r header a data1 a .... . datan a p ev1 ev3 ev3 ev3-1 ev4 s header a address a data1 a ..... datan a p ev5 ev9 ev6 ev8 ev8 ev8 s r header a data1 a ..... datan a p ev5 ev6 ev7 ev7
st72589bw, st72389bw 105/158 i 2 c bus interface (contd) 7.7.5 low power modes 7.7.6 interrupts figure 60. event flags and interrupt generation note : the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc reg- ister is reset (rim instruction). mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt 10-bit address sent event (master mode) add10 ite yes no end of byte transfer event btf yes no address matched event (slave mode) adsel yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register. add10
st72589bw, st72389bw 106/158 i 2 c bus interface (contd) 7.7.7 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: C when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 C when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. C to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). C in master mode: 0: no start generation 1: repeated start generation C in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). C in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. C in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 60 for the relationship between the events and the interrupt. scl is held low when the add10, sb, btf or adsl flags or an ev6 event (see figure 59 ) is de- tected. 70 0 0 pe engc start ack stop ite
st72589bw, st72389bw 107/158 i 2 c bus interface (contd) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 59 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: C btf=1 (byte received or transmitted) C adsl=1 (address matched in slave mode while ack=1) C sb=1 (start condition generated in master mode) C af=1 (no acknowledge received after byte transmission) C stopf=1 (stop condition detected in slave mode) C arlo=1 (arbitration lost in master mode) C berr=1 (bus error, misplaced start or stop condition detected) C add10=1 (master has sent header byte) C address byte successfully transmitted in mas- ter mode. bit 6 = add10 10-bit addressing in master mode . this bit is set by hardware when the master has sent the first byte in 10-bit address mode. it is cleared by software reading sr2 register followed by a write in the dr register of the second address byte. it is also cleared by hardware when the pe- ripheral is disabled (pe=0). 0: no add10 event occurred. 1: master has sent first address byte (header) bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. this information is still updat- ed when the interface is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). C following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 59 ). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. C following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched 70 evf add10 tra busy btf adsl m/sl sb
st72589bw, st72389bw 108/158 i 2 c bus interface (contd) bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardware when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 0 = gcal general call (slave mode). this bit is set by hardware when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal
st72589bw, st72389bw 109/158 i 2 c bus interface (contd) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc[6:0] 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). C standard mode (fm/sm=0): f scl <= 100khz f scl = f cpu /(2x([cc6..cc0]+2)) C fast mode (fm/sm=1): f scl > 100khz f scl = f cpu /(3x([cc6..cc0]+2)) note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] 8-bit data register. these bits contain the byte to be received or trans- mitted on the bus. C transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. C receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the following data bytes are received one by one after reading the dr register. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0
st72589bw, st72389bw 110/158 i 2 c bus interface (contd) i 2 c own address register (oar1) read / write reset value: 0000 0000 (00h) 7-bit addressing mode bit 7:1 = add[7:1] interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is dont care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 10-bit addressing mode bit 7:0 = add[7:0] interface address . these are the least significant bits of the i 2 c bus address of the interface. they are not cleared when the interface is disabled (pe=0). i 2 c own address register (oar2) read / write reset value: 0100 0000 (40h) bit 7:6 = fr[1:0] frequency bits. these bits are set by software only when the inter- face is disabled (pe=0). to configure the interface to i 2 c specifed delays select the value corre- sponding to the microcontroller frequency f cpu . bit 5:3 = reserved bit 2:1 = add[9:8] interface address . these are the most significant bits of the i 2 c bus address of the interface (10-bit mode only). they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. 70 add7 add6 add5 add4 add3 add2 add1 add0 70 fr1 fr0 0 0 0 add9 add8 0 f cpu fr1 fr0 < 6 mhz 0 0 6 to 8 mhz 0 1
st72589bw, st72389bw 111/158 i 2 c bus interface (contd) table 26. i 2 c register map and reset values address (hex.) register label 765 4 3210 28 i2ccr reset value 0 0 pe 0 engc 0 start 0 ack 0 stop 0 ite 0 29 i2csr1 reset value evf 0 add10 0 tra 0 busy 0 btf 0 adsl 0 m/sl 0 sb 0 2a i2csr2 reset value 0 0 0 af 0 stopf 0 arlo 0 berr 0 gcal 0 2b i2cccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 2c i2coar1 reset value add7 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 2d i2coar2 reset value fr1 0 fr0 100 0 add9 0 add8 00 2e i2cdr reset value msb 0000 000 lsb 0
st72589bw, st72389bw 112/158 7.8 controller area network (can) 7.8.1 introduction this peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in can specification rev. 2.0 part a. it can also be connected to a 2.0 b network without problems, since extended frames are checked for correctness and acknowledged accordingly although such frames cannot be trans- mitted nor received. the same applies to overload frames which are recognized but never initiated. figure 61. can block diagram tx/rx buffer 1 10 bytes tx/rx buffer 2 10 bytes tx/rx buffer 3 10 bytes id filter 0 4 bytes id filter 1 4 bytes st7 interface psr icr isr brpr csr tecr recr can 2.0b passive core shreg bcdl crc btl rx tx eml st7 internal bus btr
st72589bw, st72389bw 113/158 controller area network (contd) 7.8.2 main features C support of can specification 2.0a and 2.0b pas- sive C three prioritized 10-byte transmit/receive mes- sage buffers C two programmable global 12-bit message ac- ceptance filters C programmable baud rates up to 1 mbit/s C buffer flip-flopping capability in transmission C maskable interrupts for transmit, receive (one per buffer), error and wake-up C automatic low-power mode after 20 recessive bits or on demand (standby mode) C interrupt-driven wake-up from standby mode upon reception of dominant pulse C optional dominant pulse transmission on leaving standby mode C automatic message queuing for transmission upon writing of data byte 7 C programmable loop-back mode for self-test op- eration C advanced error detection and diagnosis func- tions C software-efficient buffer mapping at a unique ad- dress space C scalable architecture. 7.8.3 functional description 7.8.3.1 frame formats a summary of all the can frame formats is given in figure 62 for reference. it covers only the stand- ard frame format since the extended one is only acknowledged. a message begins with a start bit called start of frame (sof). this bit is followed by the arbitration field which contains the 11-bit identifier (id) and the remote transmission request bit (rtr). the rtr bit indicates whether it is a data frame or a re- mote request frame. a remote request frame does not have any data byte. the control field contains the identifier extension bit (ide), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (dlc). the data field ranges from zero to eight bytes and is followed by the cyclic redundancy check (crc) used as a frame integrity check for detecting bit errors. the acknowledgement (ack) field comprises the ack slot and the ack delimiter. the bit in the ack slot is placed on the bus by the transmitter as a re- cessive bit (logical 1). it is overwritten as a domi- nant bit (logical 0) by those receivers which have at this time received the data correctly. in this way, the transmitting node can be assured that at least one receiver has correctly received its message. note that messages are acknowledged by the re- ceivers regardless of the outcome of the accept- ance test. the end of the message is indicated by the end of frame (eof). the intermission field defines the minimum number of bit periods separating con- secutive messages. if there is no subsequent bus access by any station, the bus remains idle. 7.8.3.2 hardware blocks the can controller contains the following func- tional blocks (refer to figure 61 ): C st7 interface: buffering of the st7 internal bus and address decoding of the can registers. C tx/rx buffers: three 10-byte buffers for trans- mission and reception of maximum length mes- sages. C id filters: two 12-bit compare and dont care masks for message acceptance filtering. C psr: page selection register (see memory map). C brpr: clock divider for different data rates. C btr: bit timing register. C icr: interrupt control register. C isr: interrupt status register. C csr: general purpose control/status register. C tecr: transmit error counter register. C recr: receive error counter register. C btl: bit timing logic providing programmable bit sampling and bit clock generation for synchroni- zation of the controller. C bcdl: bit coding logic generating a nrz-coded datastream with stuff bits. C shreg: 8-bit shift register for serialization of data to be transmitted and parallelisation of re- ceived data. C crc: 15-bit crc calculator and checker. C eml: error detection and management logic. C can core: can 2.0b passive protocol control- ler.
st72589bw, st72389bw 114/158 controller area network (contd) figure 62. can frames data field 8 * n control field 6 arbitration field 12 crc field 16 ack field 7 sof id dlc crc data frame 44 + 8 * n arbitration field 12 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc control field 6 overload flag 6 overload delimiter 8 overload frame error flag 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame data frame or remote frame notes: ? 0 <= n <= 8 ? sof = start of frame ? id = identifier ? rtr = remote transmission request ? ide = identifier extension bit ? r0 = reserved bit ? dlc = data length code ? crc = cyclic redundancy code ? error flag: 6 dominant bits if node is error active else 6 recessive bits. ? suspend transmission: applies to error passive nodes only. ? eof = end of frame ? ack = acknowledge bit data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field end of frame rtr ide r0 eof
st72589bw, st72389bw 115/158 controller area network (contd) 7.8.3.3 modes of operation the can core unit assumes one of the seven states described below: C standby . standby mode is entered either on a chip reset or on resetting the run bit in the con- trol/status register (csr). any on-going trans- mission or reception operation is not interrupted and completes normally before the bit time log- ic and the clock prescaler are turned off for mini- mum power consumption. this state is signalled by the run bit being read-back as 0. once in standby, the only event monitored is the reception of a dominant bit which causes a wake- up interrupt if the scie bit of the interrupt control register (icr) is set. the standby mode is left by setting the run bit. if the wkps bit is set in the csr register, then the controller passes through wake-up otherwise it enters resync directly. it is important to note that the wake-up mecha- nism is software-driven and therefore carries a significant time overhead. all messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. C wake-up . the can bus line is forced to domi- nant for one bit time signalling the wake-up con- dition to all other bus members. figure 63. can controller state diagram n standby resync wake-up reception transmission error idle areset run run & wkps run & wkps fsyn & boff & 11 recessive bits | (fsyn | boff) & 128 * 11 recessive bits run write to data7 | tx error & nrtx start of frame arbitration lost tx error rx error tx ok rx ok boff boff
st72589bw, st72389bw 116/158 controller area network (contd) C resync . the resynchronization mode is used to find the correct entry point for starting trans- mission or reception after the node has gone asynchronous either by going into the standby or bus-off states. resynchronization is achieved when 128 se- quences of 11 recessive bits have been moni- tored unless the node is not bus-off and the fsyn bit in the csr register is set in which case a single sequence of 11 recessive bits needs to be monitored. C idle . the can controller looks for one of the fol- lowing events: the run bit is reset, a start of frame appears on the can bus or the data7 register of the currently active page is written to. C transmission . once the lock bit of a buffer control/status register (bcsrx) has been set and read back as such, a transmit job can be submitted by writing to the data7 register. the message with the highest priority will be transmit- ted as soon as the can bus becomes idle. among those messages with a pending trans- mission request, the highest priority is given to buffer 3 then 2 and 1. if the transmission fails due to a lost arbitration or to an error while the nrtx bit of the csr register is reset, then a new trans- mission attempt is performed . this goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by set- ting the nrtx bit or if the node ever enters bus- off or if a higher priority message becomes pend- ing. the rdy bit in the bcsrx register, which was set since the job was submitted, gets reset. when a transmission is in progress, the busy bit in the bcsrx register is set. if it ends successful- ly then the txif bit in the interrupt status regis- ter (isr) is set, else the teif bit is set. an interrupt is generated in either case provided the txie and teie bits of the icr register are set. the etx bit in the same register is used to get an early transmit interrupt and to automatically un- lock the transmitting buffer upon successful com- pletion of its job. this enables the cpu to get a new transmit job pending by the end of the cur- rent transmission while always leaving two buff- ers available for reception. an uninterrupted stream of messages may be transmitted in this way at no overrun risk. note 1: setting the srte bit of the csr register allows transmitted messages to be simultane- ously received when they pass the acceptance filtering. this is particularly useful for checking the integrity of the communication path. note 2: when the etx bit is reset, the buffer with the highest priority and with a pending transmis- sion request is always transmitted. when the etx bit is set, once a buffer participates in the ar- bitration phase, it is sent until it wins the arbitra- tion even if another transmission is requested from a buffer with a higher priority. C reception . once the can controller has syn- chronized itself onto the bus activity, it is ready for reception of new messages. every incoming message gets its identifier compared to the ac- ceptance filters. if the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. this buffer will be the first one - order is 1 to 3 - that has the lock and rdy bits of its bcsrx regis- ter reset. C when no such buffer exists then an overrun interrupt is generated if the orie bit of the icr register has been set. in this case the identifi- er of the last message is made available in the last identifier register (lidhr and lidlr) at least until it gets overwritten by a new identifi- er picked-up from the bus. C when a buffer does exist, the accepted mes- sage gets written into it, the acc bit in the bcsrx register gets the number of the match- ing filter, the rdy and rxif bits get set and an interrupt is generated if the rxie bit in the isr register is set. up to three messages can be automatically received without intervention from the cpu because each buffer has its own set of status bits, greatly reducing the reactiveness require- ments in the processing of the receive inter- rupts.
st72589bw, st72389bw 117/158 controller area network (contd) C error . the error management as described in the can protocol is completely handled by hard- ware using 2 error counters which get increment- ed or decremented according to the error condition. both of them may be read by the appli- cation to determine the stability of the network. moreover, as one of the node status bits (epsv or boff of the csr register) changes, an inter- rupt is generated if the scie bit is set in the icr register. refer to figure 64 . figure 64. can error state diagram error passive when tecr or recr > 127, the epsv bit gets set when tecr and recr < 128, and the epsv bit gets cleared error active bus off when tecr > 255 the boff bit gets set when 128 * 11 recessive bits occur: - the boff bit gets cleared - the tecr register gets cleared - the recr register gets cleared the epsv bit gets cleared
st72589bw, st72389bw 118/158 controller area network (contd) 7.8.3.4 bit timing logic the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronizing on following edges. its operation may be explained simply when the nominal bit time is divided into three segments as follows: C synchronisation segment (sync_seg) : a bit change is expected to lie within this time seg- ment. it has a fixed length of one time quanta (1 x t can ). C bit segment 1 (bs1) : defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can st andard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen- sate for positive phase drifts due to differences in the frequency of the various nodes of the net- work. C bit segment 2 (bs2) : defines the location of the transmit point. it represents the phase_seg2 of the can standard. its duration is programma- ble between 1 and 8 time quanta but may also be automatically shortened to compensate for neg- ative phase drifts. C resynchronization jump width (rjw) : de- fines an upper bound to the amount of lengthen- ing or shortening of the bit segments. it is programmable between 1 and 4 time quanta. to guarantee the correct behaviour of the can controller, sync_seg + bs1 + bs2 must be greater than or equal to 5 time quanta. for a detailed description of the can resynchroni- zation mechanism and other bit timing configura- tion constraints, please refer to the bosch can standard 2.0. as a safeguard against programming errors, the configuration of the bit timing register (btr) is only possible while the device is in standby mode. figure 65. bit timing sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1 x t can t bs1 t bs2 sample point transmit point
st72589bw, st72389bw 119/158 controller area network (contd) 7.8.4 register description the can registers are organized as 6 general pur- pose registers plus 5 pages of 16 registers span- ning the same address space and primarily used for message and filter storage. the page actually selected is defined by the content of the page se- lection register. refer to figure 66 . 7.8.4.1 general purpose registers interrupt status register (isr) read/write reset value: 00h bit 7 = rxif3 receive interrupt flag for buffer 3 - read/clear set by hardware to signal that a new error-free mes- sage is available in buffer 3. cleared by software to release buffer 3. also cleared by resetting bit rdy of bcsr3. bit 6 = rxif2 receive interrupt flag for buffer 2 - read/clear set by hardware to signal that a new error-free message is available in buffer 2. cleared by software to release buffer 2. also cleared by resetting bit rdy of bcsr2. bit 5 = rxif1 receive interrupt flag for buffer 1 - read/clear set by hardware to signal that a new error-free mes- sage is available in buffer 1. cleared by software to release buffer 1. also cleared by resetting bit rdy of bcsr1. bit 4 = txif transmit interrupt flag - read/clear set by hardware to signal that the highest priority message queued for transmission has been suc- cessfully transmitted (etx = 0) or that it has passed successfully the arbitration (etx = 1). cleared by software. bit 3 = scif status change interrupt flag - read/clear set by hardware to signal the reception of a domi- nant bit while in standby or a change from error ac- tive to error passive and bus-off while in run. also signals any receive error when esci = 1. cleared by software. bit 2 = orif overrun interrupt flag - read/clear set by hardware to signal that a message could not be stored because no receive buffer was available. cleared by software. bit 1 = teif transmit error interrupt flag - read/clear set by hardware to signal that an error occurred dur- ing the transmission of the highest priority message queued for transmission. cleared by software. bit 0 = epnd error interrupt pending - read only set by hardware when at least one of the three error interrupt flags scif, orif or teif is set. reset by hardware when all error interrupt flags have been cleared. caution ; interrupt flags are reset by writing a "0" to the cor- responding bit position. the appropriate way con- sists in writing an immediate mask or the ones com- plement of the register content initially read by the interrupt handler. bit manipulation instruction bres should never be used due to its read-modify- write nature. 70 rxif3 rxif2 rxif1 txif scif orif teif epnd
st72589bw, st72389bw 120/158 controller area network (contd) interrupt control register (icr) read/write reset value: 00h bit 6 = esci extended status change interrupt - read/set/clear set by software to specify that scif is to be set on receive errors also. cleared by software to set scif only on status changes and wake-up but not on all receive errors. bit 5 = rxie receive interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message has been received free of er- rors. cleared by software to disable receive interrupt re- quests. bit 4 = txie transmit interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message has been successfully trans- mitted. cleared by software to disable transmit interrupt requests. bit 3 = scie status change interrupt enable - read/set/clear set by software to enable an interrupt request whenever the nodes status changes in run mode or whenever a dominant pulse is received in standby mode. cleared by software to disable status change inter- rupt requests. bit 2 = orie overrun interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message should be stored and no re- ceive buffer is avalaible. cleared by software to disable overrun interrupt re- quests. bit 1 = teie transmit error interrupt enable - read/set/clear set by software to enable an interrupt whenever an error has been detected during transmission of a message. cleared by software to disable transmit error inter- rupts. bit 0 = etx early transmit interrupt - read/set/clear set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully. cleared by software to request the transmit inter- rupt to occur at the completion of the transfer. 70 0 esci rxie txie scie orie teie etx
st72589bw, st72389bw 121/158 controller area network (contd) control/status register (csr) read/write reset value: 00h bit 6 = boff bus-off state - read only set by hardware to indicate that the node is in bus- off state, i.e. the transmit error counter exceeds 255. reset by hardware to indicate that the node is in- volved in bus activities. bit 5 = epsv error passive state - read only set by hardware to indicate that the node is error passive. reset by hardware to indicate that the node is either error active (boff = 0) or bus-off. bit 4 = srte simultaneous receive/transmit en- able - read/set/clear set by software to enable simultaneous transmis- sion and reception of a message passing the ac- ceptance filtering. allows to check the integrity of the communication path. reset by software to discard all messages trans- mitted by the node. allows remote and data frames to share the same identifier. bit 3 = nrtx no retransmission - read/set/clear set by software to disable the retransmission of un- successful messages. cleared by software to enable retransmission of messages until success is met. bit 2 = fsyn fast synchronization - read/set/clear set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 re- cessive bits in a row. cleared by software to enable the standard resyn- chronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits. bit 1 = wkps wake-up pulse - read/set/clear set by software to generate a dominant pulse when leaving standby mode. cleared by software for no dominant wake-up pulse. bit 0 = run can enable - read/set/clear set by software to leave standby mode after 128 se- quences of 11 recessive bits or just 11 recessive bits if fsyn is set. cleared by software to request a switch to the standby or low-power mode as soon as any on-go- ing transfer is complete. read-back as 1 in the meantime to enable proper signalling of the standby state. the cpu clock may therefore be safely switched off whenever run is read as 0. 70 0 boff epsv srte nrtx fsyn wkps run
st72589bw, st72389bw 122/158 controller area network (contd) baud rate prescaler register (brpr) read/write in standby mode reset value: 00h rjw[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization. t rjw = t can * (rjw + 1) brp[5:0] determine the can system clock cycle time or time quanta which is used to build up the in- dividual bit timing. t can = t cpu * (brp + 1) where t cpu = time period of the cpu clock. the resulting baud rate can be computed by the for- mula: note: writing to this register is allowed only in standby mode to prevent any accidental can pro- tocol violation through programming errors. bit timing register (btr) read/write in standby mode reset value: 23h bs2[2:0] determine the length of bit segment 2. t bs2 = t can * (bs2 + 1) bs1[3:0] determine the length of bit segment 1. t bs1 = t can * (bs1 + 1) note: writing to this register is allowed only in standby mode to prevent any accidental can pro- tocol violation through programming errors. page selection register (psr) read/write reset value: 00h page[2:0] determine which buffer or filter page is mapped at addresses 0010h to 001fh. 70 rjw1 rjw0 brp5 brp4 brp3 brp2 brp1 brp0 br 1 t cpu brp 1 + () bs 1 bs 23 ++ () --------------------------------------------------------------------------------------------- - = 70 0 bs22 bs21 bs20 bs13 bs12 bs11 bs10 70 00000 page 2 page 1 page 0 page2 page1 page0 page title 0 0 0 diagnosis 001buffer 1 010buffer 2 011buffer 3 1 0 0 filters 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
st72589bw, st72389bw 123/158 controller area network (contd) 7.8.4.2 paged registers last identifier high register (lidhr) read/write reset value: undefined lid[10:3] are the most significant 8 bits of the last identifier read on the can bus. last identifier low register (lidlr) read/write reset value: undefined lid[2:0] are the least significant 3 bits of the last identifier read on the can bus. lrtr is the last remote transmission request bit read on the can bus. ldlc[3:0] is the last data length code read on the can bus. transmit error counter reg. (tecr) read only reset value: 00h tec[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of the fault confinement mechanism of the can protocol. in case of an error during transmission, this counter is incremented by 8. it is decremented by 1 after every successful transmission. when the counter value exceeds 127, the can controller enters the error passive state. when a value of 256 is reached, the can controller is disconnected from the bus. receive error counter reg. (recr) page: 00h read only reset value: 00h rec[7:0] is the receive error counter implement- ing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can stand- ard. after every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. identifier high registers (idhrx) read/write reset value: undefined id[10:3] are the most significant 8 bits of the 11-bit message identifier.the identifier acts as the mes- sages name, used for bus access arbitration and acceptance filtering. 70 lid10 lid9 lid8 lid7 lid6 lid5 lid4 lid3 70 lid2 lid1 lid0 lrtr ldlc 3 ldlc 2 ldlc 1 ldlc 0 70 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 70 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 70 id10id9id8id7id6id5id4id3
st72589bw, st72389bw 124/158 controller area network (contd) identifier low registers (idlrx) read/write reset value: undefined id[2:0] are the least significant 3 bits of the 11-bit message identifier. rtr is the remote transmission request bit. it is set to indicate a remote frame and reset to indicate a data frame. dlc[3:0] is the data length code. it gives the number of bytes in the data field of the mes- sage.the valid range is 0 to 8. data registers (data0-7x) read/write reset value: undefined data[7:0] is a message data byte. up to eight such bytes may be part of a message. writing to byte data7 initiates a transmit request and should al- ways be done even when data7 is not part of the message. buffer control/status regs. (bcsrx) read/write reset value: 00h bit 3 = acc acceptance code - read only set by hardware with the id of the highest priority filter which accepted the message stored in the buffer. acc = 0: match for filter/mask0. possible match for filter/mask1. acc = 1: no match for filter/mask0 and match for filter/mask1. reset by hardware when either rdy or rxif gets reset. bit 2 = rdy message ready - read/clear set by hardware to signal that a new error-free message is available (lock = 0) or that a trans- mission request is pending (lock = 1). cleared by software when lock = 0 to release the buffer and to clear the corresponding rxif bit in the interrupt status register. cleared by hardware when lock = 1 to indicate that the transmission request has been serviced or cancelled. bit 1 = busy busy buffer - read only set by hardware when the buffer is being filled (lock = 0) or emptied (lock = 1). reset by hardware when the buffer is not ac- cessed by the can core for transmission nor re- ception purposes. bit 0 = lock lock buffer - read/set/clear set by software to lock a buffer. no more message can be received into the buffer thus preserving its content and making it available for transmission. cleared by software to make the buffer available for reception. cancels any pending transmission request. cleared by hardware once a message has been successfully transmitted provided the early trans- mit interrupt mode is on. left untouched otherwise. note that in order to prevent any message corrup- tion or loss of context, lock cannot be set nor re- set while busy is set. trying to do so will result in lock not changing state. 70 id2 id1 id0 rtr dlc3 dlc2 dlc1 dlc0 70 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 70 0 0 0 0 acc rdy busy lock
st72589bw, st72389bw 125/158 controller area network (contd) filter high registers (fhrx) read/write reset value: undefined fil[11:3] are the most significant 8 bits of a 12-bit message filter. the acceptance filter is compared bit by bit with the identifier and the rtr bit of the incoming message. if there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. filter low registers (flrx) read/write reset value: undefined fil[3:0] are the least significant 4 bits of a 12-bit message filter. mask high registers (mhrx) read/write reset value: undefined msk[11:3] are the most significant 8 bits of a 12- bit message mask. the acceptance mask defines which bits of the acceptance filter should match the identifier and the rtr bit of the incoming mes- sage. msk i = 0: dont care. msk i = 1: match required. mask low registers (mlrx) read/write reset value: undefined msk[3:0] are the least significant 4 bits of a 12-bit message mask. 70 fil11 fil10 fil9 fil8 fil7 fil6 fil5 fll4 70 fil3 fil2 fil1 fil0 0 0 0 0 70 msk1 1 msk1 0 msk9 msk8 msk7 msk6 msk5 msk4 70 msk3msk2msk1msk00000
st72589bw, st72389bw 126/158 controller area network (contd) figure 66. can register map interrupt status interrupt control control/status baud rate prescaler page selection paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg0 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 6fh 5ch 5ah 5bh 5dh 5fh 60h bit timing 5eh
st72589bw, st72389bw 127/158 controller area network (contd) figure 67. page maps 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh fhr0 flr0 mhr0 mlr0 fhr1 flr1 mhr1 mlr1 reserved idhr1 idlr1 data01 data11 data21 data31 data41 data51 data61 data71 reserved bcsr1 lidhr lidlr reserved tstr tecr recr idhr2 idlr2 data02 data12 data22 data32 data42 data52 data62 data72 reserved bcsr2 idhr3 idlr3 data03 data13 data23 data33 data43 data53 data63 data73 reserved bcsr3 page 0 page 1 page 2 page 3 page 4 diagnosis buffer 1 buffer 2 buffer 3 acceptance filters
st72589bw, st72389bw 128/158 controller area network (contd) table 27. can register map and reset values address (hex.) page register label 76543210 5a canisr reset value rxif3 0 rxif2 0 rxif1 0 txif 0 scif 0 orif 0 teif 0 epnd 0 5b canicr reset value 0 esci 0 rxie 0 txie 0 scie 0 orie 0 teie 0 etx 0 5c cancsr reset value 0 boff 0 epsv 0 srte 0 nrtx 0 fsyn 0 wkps 0 run 0 5d canbrpr reset value rjw1 0 rjw0 0 brp5 0 brp4 0 brp3 0 brp2 0 brp1 0 brp0 0 5e canbtr reset value 0 bs22 0 bs21 1 bs20 0 bs13 0 bs12 0 bs11 1 bs10 1 5f canpsr reset value 0 0 0 0 0 page2 0 page1 0 page0 0 60 0 canlidhr reset value lid10 x lid9 x lid8 x lid7 x lid6 x lid5 x lid4 x lid3 x 1 to 3 canidhrx reset value id10 x id9 x id8 x id7 x id6 x id5 x id4 x id3 x 60, 64 4 canfhrx reset value fil11 x fil10 x fil9 x fil8 x fil7 x fil6 x fil5 x fil4 x 61 0 canlidlr reset value lid2 x lid1 x lid0 x lrtr x ldlc3 x ldlc2 x ldlc1 x ldlc0 x 1 to 3 canidlrx reset value id2 x id1 x id0 x rtr x dlc3 x dlc2 x dlc1 x dlc0 x 61, 65 4 canflrx reset value fil3 x fil2 x fil1 x fil0 x0000 62 to 69 1 to 3 candrx reset value msb xxxxxxx lsb x 62, 66 4 canmhrx reset value msk11 x msk10 x msk9 x msk8 x msk7 x msk6 x msk5 x msk4 x 63, 67 4 canmlrx reset value msk3 x msk2 x msk1 x msk0 x0000 6e 0 cantecr reset value msb 0 0 0000 0 lsb 0 6f canrecr reset value msb 0 0 0000 0 lsb 0 1 to 3 canbcsrx reset value 0 0 0 0 acc 0 rdy 0 busy 0 lock 0
st72589bw, st72389bw 129/158 7.9 8-bit a/d converter (adc) 7.9.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 7.9.2 main features n 8-bit conversion n up to 8 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 68 . figure 68. adc block diagram sample analog mux ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 (control status register) csr (data register) dr & hold f cpu analog to digital converter coco 0ch0 ch1 ch2 - -adon ad7 ad4 ad0 ad1 ad2 ad3 ad6 ad5
st72589bw, st72389bw 130/158 8-bit a/d converter (adc) (contd) 7.9.3 functional description the high level reference voltage v dda must be connected externally to the v dd pin. the low level reference voltage v ssa must be connected exter- nally to the v ss pin. in some devices (refer to de- vice pin out description) high and low level refer- ence voltages are internally connected to the v dd and v ss pins. conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 69. recommended ext. connections characteristics: the conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. if input voltage is greater than or equal to v dd (voltage reference high) then results = ffh (full scale) without overflow indication. if input voltage v ss (voltage reference low) then the results = 00h. the conversion time is 64 cpu clock cycles in- cluding a sampling time of 31.5 cpu clock cycles. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. the a/d converter is linear and the digital result of the conversion is given by the formula: where reference voltage is v dd - v ss . the accuracy of the conversion is described in the electrical characteristics section. procedure: refer to the csr and dr register description sec- tion for the bit definitions. each analog input pin must be configured as input, no pull-up, no interrupt. refer to the i/o ports chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: C select the ch2 to ch0 bits to assign the ana- log channel to convert. refer to table 28 channel selection . C set the adon bit. then the a/d converter is enabled after a stabilization time (typically 30 s). it then performs a continuous conversion of the selected channel. when a conversion is complete C the coco bit is set by hardware. C no interrupt is generated. C the result is in the dr register. a write to the csr register aborts the current con- version, resets the coco bit and starts a new conversion. 7.9.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed. 7.9.5 interrupts none. st7 px.x/ainx v dda v ssa v dd 0.1f r ain v ain digital result = 255 x input voltage reference voltage mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilisation time before accurate conversions can be performed.
st72589bw, st72389bw 131/158 8-bit a/d converter (adc) (contd) 7.9.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete. 1: conversion can be read from the dr register. bit 6 = reserved . must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off. 1: a/d converter is switched on. note : a typical 30 s delay time is necessary for the adc to stabilize when the adon bit is set. bit 4 = reserved . forced by hardware to 0. bit 3 = reserved . must always be cleared. bits 2:0: ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. table 28. channel selection * important note: the number of pins and the channel selection vary according to the device. refer to the device pinout). data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = ad[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. reading this register resets the coco flag. 70 coco - adon 0 - ch2 ch1 ch0 pin* ch2 ch1 ch0 ain0 000 ain1 001 ain2 010 ain3 011 ain4 100 ain5 101 ain6 110 ain7 111 70 ad7ad6ad5ad4ad3ad2ad1ad0
st72589bw, st72389bw 132/158 8-bit a/d converter (adc) (contd) table 29. adc register map and reset values address (hex.) register label 76543210 0070h adcdr reset value msb 0000000 lsb 0 0071h adccsr reset value coco 00 adon 00 0 ch2 0 ch1 0 ch0 0
st72589bw, st72389bw 133/158 8 instruction set 8.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 30. cpu addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st72589bw, st72389bw 134/158 instruction set overview (contd) 8.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 8.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 8.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 8.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 8.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st72589bw, st72389bw 135/158 instruction set overview (contd) 8.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 31. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 8.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative
st72589bw, st72389bw 136/158 instruction set overview (contd) 8.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
st72589bw, st72389bw 137/158 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
st72589bw, st72389bw 138/158 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z
st72589bw, st72389bw 139/158 9 electrical characteristics 9.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations . the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j =ta + pd x rthja where: t a = ambient temperature. rthja =package thermal resistance (junction-to ambient). p d = p int + p port . p int =i dd x v dd (chip internal power). p port =port power dissipation determined by the user) note: stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. general warning: direct connection to v dd or v ss of the reset and i/o pins could damage the device in case of un- wanted internal reset generation or program counter corruption (due to unwanted change of the i/o configuration). to guarantee safe conditions, this connection has to be done through a typical 10k w pull-up or pull-down resistor. thermal characteristics symbol ratings value unit v dd - v ss supply voltage 6.5 v v dda - v ssa analog reference voltage v dda > v ss 6.5 v v lcd max. display voltage 10.5 v |v dd_i - v dd_j | |v dd_i - v dda | max. variations (power line) 50 mv |v ss_i - v ss_j | |v ss_i - v ssa | |g lcd - v ss_i | max. variations (ground line) 50 mv v in input voltage v ss - 0.3 to v dd + 0.3 v v out output voltage v ss - 0.3 to v dd + 0.3 v esd esd susceptibility 2000 v i vdd_i total current into v dd_i (source) 80 ma i vss_i total current out of v ss_i (sink) 80 i inj total injected current +/- 5 symbol ratings value unit r thja package thermal resistance pqfp128 eqfp128 42 na c/w t jmax max. junction temperature 150 c t stg storage temperature range -65 to +150 c pd power dissipation 500 mw
st72589bw, st72389bw 140/158 9.2 recommended operating conditions note 1 : positive injection the i inj+ is done through protection diodes insulated from the substrate of the die. the pins which have a high voltage capability like true open-drain do not accept positive injection. in this case the maximum voltage rating must be followed. note 2 : adc accuracy reduced by negative injection the i inj- is done through protection diodes not insulated from the substrate of the die. the drawback is a small leakage (few a) induced inside the die when a negative injection is performed. this leakage is tolerated by the digital structure, but it acts on the analog line according to the impedance versus a leak- age current of few a (if the mcu has an ad converter). the effect depends on the pin which is submitted to the injection. of course, external digital signals applied to the component must have a maximum imped- ance close to 50k w . location of the negative current injection: - the pins with analog input capability are the more sensitive. i inj- maximum is 0.8 ma (assuming that the impedance of the analog voltage is lower than 25k w ) - the pure digital pins can tolerate 1.6ma. in addition, the best choice is to inject the current as far as pos- sible from the analog input pins. general note : when several inputs are submitted to a current injection, the maximum i inj is the sum of the positive and negative currents respectively (instantaneous values). 9.3 timing characteristics (operating conditions t a = -40 to +85c unless otherwise specified) * d t inst is the number of t cpu to finish the current instruction execution. general symbol parameter conditions min typ max unit v dd supply voltage f osc = 16mhz 4.5 5.0 5.5 v f osc oscillator frequency 4.5v < v dd < 5.5v 8 16 mhz t a ambient temperature range -40 +85 c current injection on i/o port and control pins symbol parameter conditions min typ max unit i inj+ total positive injected current (1) v external > v dd 5ma i inj- total negative injected current (2) v external < v ss digital pins analog pins 1.6 0.8 ma symbol parameter conditions min typ max unit f osc external oscillator frequency v dd = 4.5v 8 16 mhz t dog watchdog time-out f cpu = 8mhz 12,288 1.54 786,432 98.3 t cpu ms t inst instruction time 2 12 t cpu t irt interrupt reaction time t irt = d t inst + 10* 10 22 t cpu
st72589bw, st72389bw 141/158 9.4 electrical characteristics (t a =-40 to +85 o c, v dd -v ss =5v unless otherwise specified) st72e/t589bw5 (t a =-40 to +85 o c, v dd -v ss =5v unless otherwise specified) rom devices notes: 1) cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss ; clock input (osc1) driven by external square wave. 2) all i/o pins in input mode with a static value at v dd or v ss ; clock input (osc1) driven by external square wave. 3) wait mode with slow mode selected. based on characterisation results, not tested. 4) all i/o pins in input mode with a static value at v dd or v ss . symbol parameter conditions min typ. max unit v dd operating supply voltage f osc =16mhz, f cpu =8mhz 4.5 5.5 v i dd supply current in run mode 1) f osc =16mhz f cpu =8mhz 20 ma supply current in slow mode 1) f osc =16mhz f cpu =500khz 13.5 supply current in wait mode 2) f osc =16mhz f cpu =8mhz 610 supply current in slow wait mode 3) f osc =16mhz f cpu =500khz 22.5 supply current in active-halt mode 4) 0.7 supply current in halt mode 4) t a <25c 1 10 a 25c st72589bw, st72389bw 142/158 9.5 i/o ports characteristics (t a =-40 to +85 o c, voltages are referred to v ss unless otherwise specified) note: * based on characterization results. not tested. (t a =-40 to +85 o c, voltages are referred to v ss unless otherwise specified) i/o port pins (st72e/t589bw5) symbol parameter conditions min typ max unit v il input low level voltage 0.3xv dd v v ih input high level voltage 0.7xv dd v v hys schmitt trigger voltage hysteresis 400* mv v ol output low level voltage i=-5ma 1.3 v i=-2ma 0.4 v v oh output high level voltage i=5ma v dd -1.3 v i=2ma v dd -0.4 v i l input leakage current v ss st72589bw, st72389bw 143/158 9.6 supply, reset and clock characteristics the values given in the specifications are general- ly not applicable for all chips. therefore, only the limits listed below are valid for the product. the values below substitute the corresponding values in the specifications of dedicated functions. (t a =-40 to +85 o c, v dd -v ss =5v unless otherwise specified) notes :*v dd has to fall down to v tn to re-arm the por function ** por function reset the device through a pulse generation at v por . note : r smax is the equivalent serial resistance of the crystal or ceramic resonator. reset symbol parameter conditions min typ max unit r on reset weak pull-up resistance v in > v ih v in < v il 20 60 40 120 80 240 k w t pulse external reset pin pulse time 1.5 t cpu power on reset symbol parameter conditions min typ max unit v tn re-initialization level * 0.8 v v por reset generation level ** 2.0 2.6 3.4 v main external clock source symbol parameter conditions min typ max unit f osc main oscillator frequency square signal with 50% duty cycle 16 mhz v osc osc1 pin voltage v dd v main oscillator symbol parameter conditions min typ max unit f osc main oscillator frequency 8 16 mhz c li load capacitances r smax =100 w * 10 20 pf t start oscillator start-up time depends on resonator quality. a typical value is 10ms
st72589bw, st72389bw 144/158 9.7 memory and peripheral characteristics (t a =-40 to +85 o c, v dd -v ss =5v unless otherwise specified) notes : if v lcd =v lcdnominal and v dd <4.5v then v lcd dc level is applied on seg and com outputs. eprom symbol parameter conditions min typ max unit w erase uv lamp lamp wavelength 2537? 15 watt- sec/cm 2 t erase erase time uv lamp is placed 1 inch from the device window without any interposed filters 15 20 min lcd driver symbol parameter conditions min typ max unit f fr frame frequency f lcd =16384hz 64 512 hz v dcrc dc residual component v lcd =v dd no load 100 mv v coh com high level, output voltage i=50 m a, v lcd =5v i=100 m a, v lcd =10v 4.5 9.5 v v col com low level, output voltage i=100 m a, v lcd =5..10v 0.5 v soh seg high level, output voltage i=25 m a, v lcd =5v i=25 m a, v lcd =10v 4.5 9.5 v sol seg low level, output voltage i=25 m a, v lcd =5..10v 0.5 v lcd display voltage 3 10 r lcdi voltage divider resistances 1% accuracy 10 k w c lcdi voltage divider coupling capacitances 100 nf c load lcd dot load 50 pf
st72589bw, st72389bw 145/158 memory and peripheral characteristics - sci, can sci serial communication interface symbol parameter conditions typ unit f tx or f rx communication frequency (precision vs. standard ~0.16%) f cpu =8mhz standard mode tr (resp.rr)=64, pr=13 tr (resp.rr)=16, pr=13 tr (resp.rr)= 8, pr=13 tr (resp.rr)= 4, pr=13 tr (resp.rr)= 2, pr=13 tr (resp.rr)= 8, pr= 3 tr (resp.rr)= 1, pr=13 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230,77 hz extended mode etpr (resp.erpr) = 13 ~38461.54 see standard i/o port pins description for more details. can controller area network symbol parameter conditions min typ max unit f cpu frequency of operation v dd = 4.5v dc 8 mhz
st72589bw, st72389bw 146/158 memory and peripheral characteristics - spi measurement points are v ol , v oh , v il and v ih in the spi timing diagram figure 70. spi master timing diagram cpha=0, cpol=0 spi serial peripheral interface ref. symbol parameter condition value unit min. max. f spi spi frequency master slave 1/128 dc 1/4 1/2 f cpu 1t spi spi clock period master slave 4 2 t cpu 2t lead enable lead time slave 120 ns 3t lag enable lag time slave 120 ns 4t spi_h clock (sck) high time master slave 100 90 ns 5t spi_l clock (sck) low time master slave 100 90 ns 6t su data set-up time master slave 100 100 ns 7t h data hold time (inputs) master slave 100 100 ns 8t a access time (time to data active from high impedance state) slave 0 120 ns 9t dis disable time (hold time to high im- pedance state) 240 ns 10 t v data valid master (before capture edge) slave (after enable edge) 0.25 120 t cpu ns 11 t hold data hold time (outputs) master (before capture edge) slave (after enable edge) 0.25 0 t cpu ns 12 t rise rise time (20% v dd to 70% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 13 t fall fall time (70% v dd to 20% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 d7-out d6-out d0-out d7-in d6-in d0-in vr000109
st72589bw, st72389bw 147/158 memory and peripheral characteristics- spi (contd) measurement points are v ol , v oh , v il and v ih in the spi timing diagram figure 71. spi master timing diagram cpha=0, cpol=1 figure 72. spi master timing diagram cpha=1, cpol=0 figure 73. spi master timing diagram cpha=1, cpol=1 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in
st72589bw, st72389bw 148/158 memory and peripheral characteristics - spi (contd) measurement points are v ol , v oh , v il and v ih in the spi timing diagram figure 74. spi slave timing diagram cpha=0, cpol=0 figure 75. spi slave timing diagram cpha=0, cpol=1 figure 76. spi slave timing diagram cpha=1, cpol=0 figure 77. spi slave timing diagram cpha=1, cpol=1 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 54 (input) 2 3 8 9 high-z d7-out d6-out d0-out d7-in d6-in d0-in vr000112
st72589bw, st72389bw 149/158 memory and peripheral characteristics - i2c subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. figure 78. typical application with i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter standard mode i 2 c fast mode i 2 c unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 m s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 m s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 ns t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 ms c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k w sdai st72xxx scli v dd 100 w 100 w v dd 4.7k w i 2 cbus
st72589bw, st72389bw 150/158 memory and peripheral characteristics - adc warning on adc : the st72e/t589bw5 eprom devices have their adc which differs from the rom devices in term of accuracy (less precision), timing (slower stabilization and conver- sion time) and external components. care must be taken at software and hardware application levels when transferring a code from the eprom device to the rom device. oe ge 1 lsb (ideal) 1lsb ideal v dda v ssa C 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line tue =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. oe =offset error: deviation between the first actual transition and the first ideal one. ge =gain error: deviation between the last ideal transition and the last actual one. dle =differential linearity error: maximum devia- tion between actual steps and the ideal one. ile =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) tue dle ile (3) v dda v ssa adc analog to digital converter (8-bit) for st72e/t589bw5 devices symbol parameter conditions min typ max unit |tue| total unadjusted error* f adc =f cpu =4mhz v dd =v dda =5v 2 lsb oe offset error* -1 1 ge gain error* -2 2 |dle| differential linearity error* 1 |ile| integral linearity error* 2 v ain conversion range voltage v ssa v dda v i adc a/d conversion supply current f adc =f cpu =4mhz v dd =v dda =5v 1ma t stab stabilization time after enable adc 30 s t load sample capacitor loading time 8 32 s 1/f adc t conv hold conversion timeval 8 32 s 1/f adc r ain external input resistor 20 kw r adc internal input resistor 18 kw c sample sample capacitor 22 pf
st72589bw, st72389bw 151/158 memory and peripheral characteristics - adc (contd) * note : adc accuracy vs. negative injection current : for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 1 lsb by 10k w increase of the external analog source impedance. these measurements results and recommendations are done in the worst condition of injection: - negative injection - injection to an input with analog capability,adjacent to the enabled analog input - at 5v v dd supply, and worse temperature case. adc analog to digital converter (8-bit) for rom devices symbol parameter conditions min typ max unit f adc analog control frequency f adc = f cpu /2 4 mhz |tue| total unadjusted error* f cpu =8mhz, f adc =4mhz v dd =v dda =5v 1.5 lsb oe offset error* -1 1 ge gain error* -0.6 0.6 |dle| differential linearity error* 1 |ile| integral linearity error* 1.2 v ain conversion range voltage v ssa v dda v i adc a/d conversion supply current f cpu =8mhz, f adc =4mhz v dd =v dda =5v 1ma t stab stabilization time after enable adc 1 s t load sample capacitor loading time 1 4 s 1/f adc t conv hold conversion time 2 8 s 1/f adc r ain external input resistor 15 kw r adc internal input resistor 1.5 kw c sample sample capacitor 6 pf
st72589bw, st72389bw 152/158 10 package characteristics 10.1 package mechanical data figure 79. 128-pin plastic quad flat package dim. mm inches min typ max min typ max a 3.04 3.40 0.120 0.134 a1 0.25 0.33 0.010 0.013 a2 2.57 2.71 2.87 0.101 0.107 0.113 b 0.13 0.28 0.005 0.011 c 0.13 0.23 0.005 0.009 d 23.20 0.913 d1 20.00 0.787 d3 18.50 0.728 e 17.20 0.677 e1 14.00 0.551 e3 12.50 0.492 e 0.50 0.020 k 0 7 0 7 l 0.73 0.88 1.03 0.029 0.035 0.041 l1 1.60 0.063 number of pins n 128 0- 7 1.60 mm c l e b a a2 a1 d d1 d2 e e1 e2
st72589bw, st72389bw 153/158 package mechanical data (contd) figure 80. 128-pin economic quad flat package note : qualification or volume production of devices using epoxy packages (eso/edil/eqfp) is not authorized it is expressly specified that qualification and/or volume pro- duction of devices using the package e.... in any applications is not authorized. usage in any application is strictly restricted to development purpose. similar devices are available in plastic package mechanically compatible to the epoxy package for quali- fication and volume production. figure 81. recommended reflow oven profile (mid jedec) reflow soldering only dim mm inches min typ max min typ max a 2.40 0.094 a1 0.03 0.001 b 0.17 0.22 0.27 0.007 0.009 0.011 d 23.00 23.20 23.40 0.906 0.913 0.921 d1 18.57 18.72 18.97 0.731 0.737 0.747 e 17.00 17.20 17.40 0.669 0.677 0.685 e1 12.57 12.72 12.97 0.495 0.501 0.511 e 0.50 0.020 g 13.60 0.535 g1 19.60 0.772 g2 1.80 0.071 l 1.40 0.055 l1 1.60 0.063 ?n 0.35 0.014 ?p 1.10 0.043 number of pins n 128 (nd=38 / ne=26) eqfp128 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec
st72589bw, st72389bw 154/158 11 device configuration and ordering information 11.1 ordering information and transfer of customer code customer code is made up of the fastrom or rom contents and the list of the selected options (if any). the fastrom or rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. see page 155 . the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 32. ordering information note 1. /xxx stands for the rom or fastrom code name assigned by stmicroelectronics. sales type 1) program memory (bytes) ram (bytes) package st72389bw4/xxx 16k rom 512 pqfp128 ST72P589BW5/xxx 24k fastrom 1024 st72t589bw5 24k otp
st72589bw, st72389bw 155/158 microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom or fastrom code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *the rom or fastrom code name is assigned by stmicroelectronics. rom or fastrom code must be sent in .s19 format. .hex extension cannot be processed. stmicroelectronics references: device: [ ] st72p589b (24 kb) [ ] st72389b (16 kb) temperature range: [ ] 0 c to +70 c [ ] -40 c to +85 c package: [ ] pqfp128: [ ] tape & reel [ ] tray marking: [ ] standard marking: [ ] special marking (rom only): pqfp128 (14 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ authorized characters are letters, digits, ., -, / and spaces only. please consult your local stmicroelectronics sales office for other marking details if required. comments: notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
st72589bw, st72389bw 156/158 11.2 st7 application notes identification description example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripheral registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 application to st72f264 product optimization
st72589bw, st72389bw 157/158 an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1477 emulated data eeprom with xflash memory an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscil- lator programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus identification description
st72589bw, st72389bw 158/158 12 summary of changes description of the changes between the current release of the specification and the previous one. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com rev. main changes date 2.7 changed output configuration for pd4 and pd5 in table 1, device pin description, on page 6 removed references to 32-khz auxiliary oscillator added notes: i2c, pwm-brm and can available on st72589 version only added v hys in section 9.5 on page 142 june 03

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